MC9S12NE64VTUE Freescale Semiconductor, MC9S12NE64VTUE Datasheet - Page 66
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MC9S12NE64VTUE
Manufacturer Part Number
MC9S12NE64VTUE
Description
IC MCU 64K FLASH EEPROM 80-TQFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.MC9S12NE64VTU.pdf
(554 pages)
Specifications of MC9S12NE64VTUE
Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, Ethernet, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
38
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.375 V ~ 3.465 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
80-TQFP Exposed Pad, 80-eTQFP, 80-HTQFP, 80-VQFP
Processor Series
S12N
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
125 MHz
Number Of Programmable I/os
70
Number Of Timers
4
Operating Supply Voltage
- 0.3 V to + 3 V
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
EVB9S12NE64E, DEMO9S12NE64E
Minimum Operating Temperature
- 65 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
HCS12
Device Core Size
16b
Frequency (max)
25MHz
Total Internal Ram Size
8KB
# I/os (max)
70
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
2.625/3.465V
Operating Supply Voltage (min)
2.357/2.375/3.135V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 105C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
TQFP
For Use With
EVB9S12NE64E - BOARD EVAL FOR 9S12NE64DEMO9S12NE64E - DEMO BOARD FOR 9S12NE64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC9S12NE64VTUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9S12NE64VTUE
Manufacturer:
FREESCALE
Quantity:
20 000
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Chapter 1 MC9S12NE64 Device Overview
1.7.5.3.2
During system low-power stop mode, the EMAC is immediately disabled. Any receive in progress is
dropped and any PAUSE time-out is cleared. The user must not to enter low-power stop mode when
TXACT or BUSY are set.
1.7.6
See the EPHY chapter for information about the Ethernet physical transceiver module. The EPHY also has
MII register space which is not part of the MCU address space and not accessible via the IP bus. The MII
registers can be accessed using the MDIO functions of the EMAC when the EMAC is configured for
internal PHY operation. The MII pins of the EPHY are not externally accessible. All communication and
management of the EPHY must be performed using the EMAC.
The organization unique identifier (OUI) for the MC9S12NE64 is 00-60-11 (hex).
1.7.6.1
Special care must be taken when executing STOP and WAIT instructions while using the EPHY or
undesired operation may result.
1.7.6.1.1
Transmit and receive operations are not possible in wait mode if the CWAI bit is set in the CLKSEL
register because the clocks to the internal MII interface are stopped.
1.7.6.1.2
During system low-power stop mode, the EPHY is immediately reset and powered down. Upon exiting
stop mode, the a start-up delay is required prior to initiating MDIO communications with the EPHY. See
A.14, “EPHY Electrical
the system from stop mode.
1.7.7
This module supports single-cycle misaligned word accesses without wait states.
In addition to operating as the CPU storage, the 8K system RAM also functions as the Ethernet buffer
while the EMAC module is enabled. While the EMAC is enabled, the Ethernet buffer will occupy 0.375K
to 4.5K of RAM with physical addresses starting at $0000 and ending at $017F up to $11FF, depending
on the setting of the BUFMAP bits in the EMAC Ethernet buffer configuration register (BUFCFG). The
relative RAM address, which are controlled by settings in the internal RAM position register (INTRM),
must be tracked in software.
The Ethernet buffer operation of the RAM is independent of the CPU and allows same cycle read/write
access from the CPU and the EMAC. No hardware blocking mechanism is implemented to prevent the
CPU from accessing the Ethernet RAM space, so care must be taken to ensure that the CPU does not
corrupt the RAM Ethernet contents.
66
RAM 8K Block Description
Ethernet Physical Transceiver (EPHY)
Low-Power Operation
Stop
Wait
Stop
Characteristics” for details. It is not possible to use an EPHY interrupt to wake
MC9S12NE64 Data Sheet, Rev 1.0
Freescale Semiconductor
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