MC56F8147VPYE Freescale Semiconductor, MC56F8147VPYE Datasheet - Page 117

• Manufacturer Part Number: MC56F8147VPYE
• Description: IC DSP 16BIT 40MHZ 160-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8147VPYE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 160-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Data Ram Size: 4 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4 x 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.5.10
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short
address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;
the upper address bits are not directly controllable. This register set allows limited control of the full
address, as shown in
Note:
With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral
registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register
to its previous contents prior to returning from interrupt.
Note:
Note:
6.5.10.1
This field represents the upper two address bits of the “hard coded” I/O short address.
Freescale Semiconductor
Preliminary
Base + $D
RESET
Write
Read
I/O Short Address Location Register (SIM_ISALH and SIM_ISALL)
If this register is set to something other than the top of memory (EOnCE register space) and the EX bit
in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions
will be affected.
The default value of this register set points to the EOnCE registers.
The pipeline delay between setting this register set and using short I/O addressing with the new value
is three cycles.
Input/Output Short Address Low (ISAL[23:22])—Bit 1–0
Figure 6-14 I/O Short Address Location High Register (SIM_ISALH)
Full 24-Bit for Short I/O Address
2 bits from SIM_ISALH Register
15
1
1
16 Bits from SIM_ISALL Register
Figure
14
1
1
Figure 6-13 I/O Short Address Determination
13
6-13.
1
1
6 Bits from I/O Short Address Mode Instruction
12
1
1
56F8347 Technical Data, Rev.11
11
1
1
“
10
1
1
Hard Coded” Address Portion
9
1
1
8
1
1
7
1
1
6
1
1
5
1
1
Instruction Portion
4
1
1
3
1
1
2
1
1
Register Descriptions
ISAL[23:22]
1
1
0
1
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