MC56F8147VPYE Freescale Semiconductor, MC56F8147VPYE Datasheet - Page 25

• Manufacturer Part Number: MC56F8147VPYE
• Description: IC DSP 16BIT 40MHZ 160-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8147VPYE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 160-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Data Ram Size: 4 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4 x 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Preliminary
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
Signal Name
(GPIOD8)
(GPIOD9)
(CS0)
(CS1)
WR
PS
DS
Pin
No.
51
53
54
Ball
No.
N6
L4
L5
Output
Output
Output
Output
Output
Input/
Input/
Type
56F8347 Technical Data, Rev.11
disabled,
pull-up is
disabled,
pull-up is
disabled,
pull-up is
output is
output is
output is
In reset,
enabled
In reset,
enabled
In reset,
enabled
During
Reset
State
Write Enable — WR is asserted during external memory
write cycles. When WR is asserted low, pins D0 - D15
become outputs and the device puts data on the bus. When
WR is deasserted high, the external data is latched inside
the external device. When WR is asserted, it qualifies the A0
- A16, PS, and DS pins. WR can be connected directly to the
WE pin of a static RAM.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), WR is tri-stated when the external bus is
inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
To deactivate the internal pull-up resistor, set the CTRL bit in
the SIM_PUDR register.
Program Memory Select — This signal is actually CS0 in
the EMI, which is programmed at reset for compatibility with
the 56F80x PS signal. PS is asserted low for external
program memory access.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), CS0 is tri-stated when the external bus is
inactive.
CS0 resets to provide the PS function as defined on the
56F80x devices.
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
To deactivate the internal pull-up resistor, clear bit 8 in the
GPIOD_PUR register.
Data Memory Select — This signal is actually CS1 in the
EMI, which is programmed at reset for compatibility with the
56F80x DS signal. DS is asserted low for external data
memory access.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), A0 - A23 and EMI control signals are
tri-stated when the external bus is inactive.
CS1 resets to provide the DS function as defined on the
56F80x devices.
Port D GPIO — This GPIO pin can be individually
programmed as an input or output pin.
To deactivate the internal pull-up resistor, clear bit 9 in the
GPIOD_PUR register.
Signal Description
Signal Pins
25