MC56F8147VPYE Freescale Semiconductor, MC56F8147VPYE Datasheet - Page 136

IC DSP 16BIT 40MHZ 160-LQFP

MC56F8147VPYE

Manufacturer Part Number
MC56F8147VPYE
Description
IC DSP 16BIT 40MHZ 160-LQFP
Manufacturer
Freescale Semiconductor
Series
56F8xxxr
Datasheet

Specifications of MC56F8147VPYE

Core Processor
56800
Core Size
16-Bit
Speed
40MHz
Connectivity
EBI/EMI, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
76
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Ram Size
4K x 16
Voltage - Supply (vcc/vdd)
2.25 V ~ 3.6 V
Data Converters
A/D 16x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 105°C
Package / Case
160-LQFP
Data Bus Width
16 bit
Processor Series
MC56F81xx
Core
56800E
Data Ram Size
4 KB
Interface Type
SPI, SCI, CAN
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
76
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
4 x 12 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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10.3 AC Electrical Characteristics
Tests are conducted using the input levels specified in
propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured
between the 10% and 90% points, as shown in
Figure 10-2
10.4 Flash Memory Characteristics
136
1. There is additional overhead which is part of the programming sequence. See the 56F8300 Peripheral User Manual
2. Specifies page erase time. There are 512 bytes per page in the Data and Boot Flash memories. The Program Flash
Characteristic
Program time
Erase time
Mass erase time
for details. Program time is per 16-bit word in Flash memory. Two words at a time can be programmed within the Pro-
gram Flash module, as it contains two interleaved memories.
module uses two interleaved Flash memories, increasing the effective page size to 1024 bytes.
Input Signal
Note: The midpoint is V
Active state, when a bus or signal is driven, and enters a low impedance state
Tri-stated, when a bus or signal is placed in a high impedance state
Data Valid state, when a signal level has reached V
Data Invalid state, when a signal level is in transition between V
Data Invalid State
shows the definitions of the following signal states:
2
1
Data1 Valid
Data1
Figure 10-1 Input Signal Measurement References
Fall Time
IL
+ (V
Data Active
Midpoint1
Table 10-12 Flash Timing Parameters
IH
V
– V
IH
IL
Figure 10-2 Signal States
)/2.
56F8347 Technical Data, Rev.11
Data2 Valid
Symbol
T
T
Data2
T
erase
prog
me
Figure
Low
V
IL
OL
10-1.
Min
100
20
20
or V
Tri-stated
OH
Data
Table
OL
Typ
Rise Time
10-5. Unless otherwise specified,
and V
High
OH
Data3 Valid
Data Active
Data3
Max
Freescale Semiconductor
90%
50%
10%
Unit
ms
ms
μs
Preliminary

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