MC56F8147VPYE Freescale Semiconductor, MC56F8147VPYE Datasheet - Page 139

• Manufacturer Part Number: MC56F8147VPYE
• Description: IC DSP 16BIT 40MHZ 160-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8147VPYE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 160-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Data Ram Size: 4 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4 x 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DCAOE and DCAEO are calculated as follows:
The timing of write cycles is different when WWS = 0 than when WWS > 0. Therefore, some parameters
contain two sets of numbers to account for this difference. Use the “Wait States Configuration” column
of
Note:
Freescale Semiconductor
Preliminary
Table 10-16
A0-Axx,CS
D0-D15
DCAOE =
DCAEO =
WR
RD
When multiple lines are given for the same wait state configuration, calculate each and then select the
smallest or most negative.
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
to make the appropriate selection.
=
=
Example of DCAOE and DCAEO calculation:
Assuming prescaler is set for ÷ 1 and prescaler clock is selected by ZSRC, if XTAL duty cycle
ranges between 45% and 60% high;
DCAOE = .50 - .60 = - 0.1
DCAEO = .45 - .50 = - 0.05
0.5 - MAX XTAL duty cycle, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1
0.0 all other cases
MIN XTAL duty cycle - 0.5, if ZSRC selects prescaler clock and the prescaler is set to ÷ 1
0.0 all other cases
Figure 10-4 External Memory Interface Timing
t
WRWR
t
AWR
t
DWR
t
Data Out
DOS
56F8347 Technical Data, Rev.11
t
WR
t
DOH
t
WAC
t
WRRD
t
ARDA
t
AD
t
ARDD
t
RDD
t
RD
Data In
External Memory Interface Timing
t
DRD
t
RDA
t
RDRD
t
RDWR
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