MC56F8147VPYE Freescale Semiconductor, MC56F8147VPYE Datasheet - Page 4

• Manufacturer Part Number: MC56F8147VPYE
• Description: IC DSP 16BIT 40MHZ 160-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8147VPYE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: EBI/EMI, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 76
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Ram Size: 4K x 16
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 160-LQFP
• Data Bus Width: 16 bit
• Processor Series: MC56F81xx
• Core: 56800E
• Data Ram Size: 4 KB
• Interface Type: SPI, SCI, CAN
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 76
• Number Of Timers: 2
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4 x 12 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Part 1: Overview. . . . . . . . . . . . . . . . . . . . . . . 5
Part 2: Signal/Connection Descriptions . . . 15
Part 3: On-Chip Clock Synthesis (OCCS) . 38
Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 40
Part 5: Interrupt Controller (ITCN) . . . . . . . 74
Part 6: System Integration Module (SIM) . 103
Part 7: Security Features . . . . . . . . . . . . . . 120
4
1.1. 56F8347/56F8147 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . 9
1.4. Architecture Block Diagram . . . . . . . . . . . . . 10
1.5. Product Documentation . . . . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions . . . . . . . . . . . . . . 14
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.2. External Clock Operation . . . . . . . . . . . . . . 38
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.2. Program Map. . . . . . . . . . . . . . . . . . . . . . . . 41
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 42
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 46
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 47
4.7. Peripheral Memory Mapped Registers . . . . 48
4.8. Factory Programmed Memory. . . . . . . . . . . 73
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3. Functional Description . . . . . . . . . . . . . . . . 74
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 76
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . 76
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 77
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . . 104
6.4. Operating Mode Register . . . . . . . . . . . . . 104
6.5. Register Descriptions . . . . . . . . . . . . . . . . 105
6.6. Clock Generation Overview. . . . . . . . . . . . 118
6.7. Power-Down Modes Overview . . . . . . . . . 118
6.8. Stop and Wait Mode Disable Function . . . 119
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.1. Operation with Security Enabled . . . . . . . 120
7.2. Flash Access Blocking Mechanisms . . . . . 120
56F8347 Technical Data, Rev.11
Table of Contents
Part 8: General Purpose Input/Output
Part 9: Joint Test Action Group (JTAG) . 128
Part 10: Specifications. . . . . . . . . . . . . . . . 128
Part 11: Packaging . . . . . . . . . . . . . . . . . . . 156
Part 12: Design Considerations . . . . . . . . 167
Part 13: Ordering Information . . . . . . . . . . 170
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 123
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 123
8.3. Configuration. . . . . . . . . . . . . . . . . . . . . . . 123
9.1. JTAG Information . . . . . . . . . . . . . . . . . . . 128
10.1. General Characteristics. . . . . . . . . . . . . . 128
10.2. DC Electrical Characteristics . . . . . . . . . . 132
10.3. AC Electrical Characteristics . . . . . . . . . . 136
10.4. Flash Memory Characteristics. . . . . . . . . 136
10.5. External Clock Operation Timing . . . . . . 137
10.6. Phase Locked Loop Timing. . . . . . . . . . . . 137
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 138
10.8. External Memory Interface Timing . . . . . . 138
10.9. Reset, Stop, Wait, Mode Select,
10.10. Serial Peripheral Interface (SPI) Timing . 143
10.11. Quad Timer Timing . . . . . . . . . . . . . . . . 147
10.12. Quadrature Decoder Timing . . . . . . . . . . 147
10.13. Serial Communication Interface
10.14. Controller Area Network (CAN) Timing . 149
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 149
10.16. Analog-to-Digital Converter
10.17. Equivalent Circuit for ADC Inputs . . . . . 154
10.18. Power Consumption . . . . . . . . . . . . . . . 154
11.1. 56F8347 Package and Pin-Out
11.2. 56F8147 Package and Pin-Out
12.1. Thermal Design Considerations . . . . . . . . 167
12.2. Electrical Design Considerations . . . . . . . 168
12.3. Power Distribution and I/O Ring
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . 123
and Interrupt Timing . . . . . . . . . . 141
(SCI) Timing . . . . . . . . . . . . . . . . 148
(ADC) Parameter . . . . . . . . . . . . 151
Information . . . . . . . . . . . . . . . . . 156
Information . . . . . . . . . . . . . . . . . 163
Implementation . . . . . . . . . . . . . . 169
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