ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 105

• Manufacturer Part Number: ATSAM3S4CA-AU
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 79
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Cpu Family: AT91
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 64MHz
• Total Internal Ram Size: 48KB
• # I/os (max): 79
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.62V
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.13.1
10.13.1.1
10.13.1.2
10.13.1.3
6500C–ATARM–8-Feb-11
ADD, ADC, SUB, SBC, and RSB
Syntax
Operation
Restrictions
Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract.
where:
op
S
result of the operation, see
cond
Rd
Rn
Operand2
imm12
The ADD instruction adds the value of Operand2 or imm12 to the value in Rn.
The ADC instruction adds the values in Rn and Operand2, together with the carry flag.
The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn.
The SBC instruction subtracts the value of Operand2 from the value in Rn. If the carry flag is
clear, the result is reduced by one.
The RSB instruction subtracts the value in Rn from the value of Operand2. This is useful
because of the wide range of options for Operand2.
Use ADC and SBC to synthesize multiword arithmetic, see
page
See also
ADDW is equivalent to the ADD syntax that uses the imm12 operand. SUBW is equivalent to the
SUB syntax that uses the imm12 operand.
In these instructions:
• Operand2 must not be SP and must not be PC
op{S}{cond} {Rd,} Rn, Operand2
op{cond} {Rd,} Rn, #imm12
107.
ADD
ADC
SUB
SBC
RSB
“ADR” on page
is one of:
Add.
Add with Carry.
Subtract.
Subtract with Carry.
Reverse Subtract.
is an optional suffix. If S is specified, the condition code flags are updated on the
is an optional condition code, see
is the destination register. If Rd is omitted, the destination register is Rn.
is the register holding the first operand.
is a flexible second operand.
See
is any value in the range 0-4095.
“Flexible second operand” on page 80
88.
“Conditional execution” on page
“Conditional execution” on page
; ADD and SUB only
for details of the options.
SAM3S Preliminary
84.
“Multiword arithmetic examples” on
84.
105