ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 130

• Manufacturer Part Number: ATSAM3S4CA-AU
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 79
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Cpu Family: AT91
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 64MHz
• Total Internal Ram Size: 48KB
• # I/os (max): 79
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.62V
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.17.1
10.17.1.1
10.17.1.2
10.17.1.3
130
SAM3S Preliminary
B, BL, BX, and BLX
Syntax
Operation
Restrictions
Branch instructions.
where:
B
BL
BX
BLX
cond
label
Rm
be 1, but the address to branch to is created by changing bit[0] to 0.
All these instructions cause a branch to label, or to the address indicated in Rm. In addition:
Bcond label is the only conditional instruction that can be either inside or outside an IT block. All
other branch instructions must be conditional inside an IT block, and must be unconditional out-
side the IT block, see
Table 10-24
Table 10-24. Branch ranges
You might have to use the .W suffix to get the maximum branch range. See
selection” on page
The restrictions are:
Instruction
B label
Bcond label
Bcond label
BL{cond} label
BX{cond} Rm
BLX{cond} Rm
• The BL and BLX instructions write the address of the next instruction to LR (the link register,
• The BX and BLX instructions cause a UsageFault exception if bit[0] of Rm is 0.
R14).
B{cond} label
BL{cond} label
BX{cond} Rm
BLX{cond} Rm
(outside IT block)
(inside IT block)
shows the ranges for the various branch instructions.
is branch (immediate).
is branch with link (immediate).
is branch indirect (register).
is branch indirect with link (register).
is an optional condition code, see
is a PC-relative expression. See
is a register that indicates an address to branch to. Bit[0] of the value in Rm must
86.
“IT” on page
Any value in register
Any value in register
Branch range
− 16 MB to +16 MB
− 1 MB to +1 MB
− 16 MB to +16 MB
− 16 MB to +16 MB
133.
“PC-relative expressions” on page
“Conditional execution” on page
6500C–ATARM–8-Feb-11
“Instruction width
84.
84.