ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 85

• Manufacturer Part Number: ATSAM3S4CA-AU
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 79
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Cpu Family: AT91
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 64MHz
• Total Internal Ram Size: 48KB
• # I/os (max): 79
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.62V
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.11.7.1
10.11.7.2
6500C–ATARM–8-Feb-11
The condition flags
Condition code suffixes
This section describes:
The APSR contains the following condition flags:
N
Z
C
V
For more information about the APSR see
A carry occurs:
Overflow occurs if the result of an add, subtract, or compare is greater than or equal to 2
less than –2
Most instructions update the status flags only if the S suffix is specified. See the instruction
descriptions for more information.
The instructions that can be conditional have an optional condition code, shown in syntax
descriptions as {cond}. Conditional execution requires a preceding IT instruction. An instruction
with a condition code is only executed if the condition code flags in the APSR meet the specified
condition.
You can use conditional execution with the IT instruction to reduce the number of branch instruc-
tions in code.
Table 10-16
flags.
Table 10-16. Condition code suffixes
Suffix
EQ
NE
CS or
HS
CC or
LO
MI
PL
VS
•
•
• if the result of an addition is greater than or equal to 2
• if the result of a subtraction is positive or zero
• as the result of an inline barrel shifter operation in a move or logical instruction.
“The condition flags”
“Condition code suffixes”
Table 10-16
Flags
Z = 1
Z = 0
C = 1
C = 0
N = 1
N = 0
V = 1
31
also shows the relationship between condition code suffixes and the N, Z, C, and V
.
Set to 1 when the result of the operation was negative, cleared to 0 otherwise.
Set to 1 when the result of the operation was zero, cleared to 0 otherwise.
Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.
Set to 1 when the operation caused overflow, cleared to 0 otherwise.
shows the condition codes to use.
.
Meaning
Equal
Not equal
Higher or same, unsigned ≥
Lower, unsigned <
Negative
Positive or zero
Overflow
“Program Status Register” on page
32
SAM3S Preliminary
45.
31
, or
85