ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 865
![IC MCU 32BIT 256KB FLASH 100LQFP](/photos/6/76/67646/313-100-lqfp_sml.jpg)
ATSAM3S4CA-AU
Manufacturer Part Number
ATSAM3S4CA-AU
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4CA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
79
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 16x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
79
Ram Memory Size
48KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Cpu Family
AT91
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
64MHz
Total Internal Ram Size
48KB
# I/os (max)
79
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.62V
On-chip Adc
16-chx12-bit
On-chip Dac
2-chx12-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4CA-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- Current page: 865 of 1118
- Download datasheet (24Mb)
6500C–ATARM–8-Feb-11
Sequence for Method 3:
1. Select the automatic write of duty-cycle values and automatic update by setting the field
2. Define the synchronous channels by the bits SYNCx in the PWM_SCM register.
3. Define the update period by the field UPR in the PWM_SCUP register.
4. Define when the WRDY flag and the corresponding PDC transfer request must be set in
5. Define the PDC transfer settings for the duty-cycle values and enable it in the PDC
6. Enable the synchronous channels by writing CHID0 in the PWM_ENA register.
7. If an update of the period value and/or of the dead-time values is required, write regis-
8. Set UPDULOCK to 1 in PWM_SCUC.
9. The update of these registers will occur at the beginning of the next PWM period. At
10. If an update of the update period value is required, check first that write of a new update
11. Write the register that needs to be updated (PWM_SCUPUPD).
12. The update of this register will occur at the next PWM period of the synchronous chan-
13. Check the end of the PDC transfer by the flag ENDTX. If the transfer has ended, define
UPDM to 2 in the PWM_SCM register.
the update period by the PTRM bit and the PTRCS field in the PWM_SCM register (at
the end of the update period or when a comparison matches).
registers
ters that need to be updated (PWM_CPRDUPDx, PWM_DTUPDx), else go to
this moment the bit UPDULOCK is reset, go to
value is possible by polling the flag WRDY (or by waiting for the corresponding inter-
rupt) in the PWM_ISR2 register, else go to
nels when the Update Period is elapsed. Go to
a new PDC transfer in the PDC registers for new duty-cycle values. Go to
Step 13.
Step 7.
Step 10.
SAM3S Preliminary
for new values.
for new values.
Step 5.
Step 10.
865
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