ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 172

IC MCU 32BIT 256KB FLASH 100LQFP

ATSAM3S4CA-AU

Manufacturer Part Number
ATSAM3S4CA-AU
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Atmel
Series
SAM3Sr
Datasheets

Specifications of ATSAM3S4CA-AU

Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
79
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 16x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
79
Ram Memory Size
48KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Cpu Family
AT91
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
64MHz
Total Internal Ram Size
48KB
# I/os (max)
79
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.62V
On-chip Adc
16-chx12-bit
On-chip Dac
2-chx12-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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• VECTCLRACTIVE
WO
Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is
Unpredictable.
• VECTRESET
WO
Reserved for Debug use. This bit reads as 0. When writing to the register you must write 0 to this bit, otherwise behavior is
Unpredictable.
10.21.6.1
172
SAM3S Preliminary
Binary point
The PRIGROUP field indicates the position of the binary point that splits the PRI_n fields in the
Interrupt Priority Registers into separate group priority and subpriority fields.
how the PRIGROUP value controls this split.
Table 10-31. Priority grouping
1.
Determining preemption of an exception uses only the group priority field, see
grouping” on page
PRIGROUP
b011
b100
b101
b110
b111
PRI_n[7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a sub-
priority field bit.
Interrupt priority level value, PRI_N[7:0]
Binary
point
bxxxx.0000
bxxx.y0000
bxx.yy0000
bx.yyy0000
b.yyyy0000
68.
(1)
Group priority
bits
[7:4]
[7:5]
[7:6]
[7]
None
Subpriority
bits
None
[4]
[5:4]
[6:4]
[7:4]
Number of
Group
priorities
16
8
4
2
1
Table 10-31
6500C–ATARM–8-Feb-11
“Interrupt priority
Subpriorities
1
2
4
8
16
shows

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