ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 179

• Manufacturer Part Number: ATSAM3S4CA-AU
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 79
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Cpu Family: AT91
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 64MHz
• Total Internal Ram Size: 48KB
• # I/os (max): 79
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.62V
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

10.21.10 System Handler Control and State Register
• USGFAULTENA
Usage fault enable bit, set to 1 to enable
• BUSFAULTENA
Bus fault enable bit, set to 1 to enable
• MEMFAULTENA
Memory management fault enable bit, set to 1 to enable
• SVCALLPENDED
SVC call pending bit, reads as 1 if exception is pending
• BUSFAULTPENDED
Bus fault exception pending bit, reads as 1 if exception is pending
• MEMFAULTPENDED
Memory management fault exception pending bit, reads as 1 if exception is pending
• USGFAULTPENDED
Usage fault exception pending bit, reads as 1 if exception is pending
• SYSTICKACT
SysTick exception active bit, reads as 1 if exception is active
• PENDSVACT
PendSV exception active bit, reads as 1 if exception is active
1.
2.
3.
6500C–ATARM–8-Feb-11
SVCALLPENDE
SVCALLAVCT
31
23
15
D
7
Enable bits, set to 1 to enable the exception, or set to 0 to disable the exception.
Pending bits, read as 1 if the exception is pending, or as 0 if it is not pending. You can write to these bits to change the pending
Active bits, read as 1 if the exception is active, or as 0 if it is not active. You can write to these bits to change the active status of
status of the exceptions.
the exceptions, but see the Caution in this section.
BUSFAULTPEND
ED
30
22
14
6
The SHCSR enables the system handlers, and indicates:
See the register summary in
ments are:
• the pending status of the bus fault, memory management fault, and SVC exceptions
• the active status of the system handlers.
MEMFAULTPEN
Reserved
Reserved
DED
29
21
13
5
(3)
(1)
USGFAULTPEND
28
20
12
ED
4
Table 10-30 on page 164
(2)
(3)
Reserved
(3)
USGFAULTACT
SYSTICKACT
(2)
27
19
11
3
(2)
USGFAULTENA
PENDSVACT
Reserved
for the SHCSR attributes. The bit assign-
26
18
10
2
(2)
SAM3S Preliminary
BUSFAULTENA
BUSFAULTACT
Reserved
25
17
9
1
MEMFAULTENA
MEMFAULTACT
MONITORACT
24
16
8
0
179