ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 517
![IC MCU 32BIT 256KB FLASH 100LQFP](/photos/6/76/67646/313-100-lqfp_sml.jpg)
ATSAM3S4CA-AU
Manufacturer Part Number
ATSAM3S4CA-AU
Description
IC MCU 32BIT 256KB FLASH 100LQFP
Manufacturer
Atmel
Series
SAM3Sr
Specifications of ATSAM3S4CA-AU
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
64MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
79
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 1.95 V
Data Converters
A/D 16x10/12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Controller Family/series
ATSAM3S
No. Of I/o's
79
Ram Memory Size
48KB
Cpu Speed
64MHz
No. Of Timers
6
Rohs Compliant
Yes
Processor Series
ATSAM3x
Core
ARM Cortex M3
3rd Party Development Tools
JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
ATSAM3S-EK
Cpu Family
AT91
Device Core
ARM Cortex-M3
Device Core Size
32b
Frequency (max)
64MHz
Total Internal Ram Size
48KB
# I/os (max)
79
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.62V
On-chip Adc
16-chx12-bit
On-chip Dac
2-chx12-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATSAM3S4CA-AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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28.7.28
Name:
Addresses:
Access:
• P0-P31: Glitch or Debouncing Filter Selection Status
0 = The Glitch Filter is able to filter glitches with a duration < Tmck2.
1 = The Debouncing Filter is able to filter pulses with a duration < Tdiv_slclk/2.
28.7.29
Name:
Addresses:
Access:
• DIVx: Slow Clock Divider Selection for Debouncing
Tdiv_slclk = 2*(DIV+1)*Tslow_clock.
6500C–ATARM–8-Feb-11
6500C–ATARM–8-Feb-11
DIV7
P31
P23
P15
P7
31
23
15
31
23
15
7
7
-
-
-
PIO Input Filter Slow Clock Status Register
PIO Slow Clock Divider Debouncing Register
DIV6
P30
P22
P14
P6
30
22
14
30
22
14
PIO_IFSCSR
0x400E0E88 (PIOA), 0x400E1088 (PIOB), 0x400E1288 (PIOC)
Read-only
6
PIO_SCDR
0x400E0E8C (PIOA), 0x400E108C (PIOB), 0x400E128C (PIOC)
Read-write
6
-
-
-
DIV13
DIV5
P29
P21
P13
P5
29
21
13
29
21
13
5
5
-
-
DIV12
DIV4
P28
P20
P12
P4
28
20
12
28
20
12
4
4
-
-
DIV11
DIV3
P27
P19
P11
P3
27
19
11
27
19
11
3
3
-
-
DIV10
DIV2
P26
P18
P10
P2
26
18
10
26
18
10
2
2
-
-
SAM3S Preliminary
SAM3S Preliminary
DIV9
DIV1
P25
P17
P9
P1
25
17
25
17
9
1
9
1
-
-
DIV8
DIV0
P24
P16
P8
P0
24
16
24
16
8
0
8
0
-
-
517
517
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