ATSAM3S4CA-AU Atmel, ATSAM3S4CA-AU Datasheet - Page 433

• Manufacturer Part Number: ATSAM3S4CA-AU
• Description: IC MCU 32BIT 256KB FLASH 100LQFP
• Manufacturer: Atmel
• Series: SAM3Sr

Specifications of ATSAM3S4CA-AU

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 79
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 1.95 V
• Data Converters: A/D 16x10/12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: ATSAM3S
• No. Of I/o's: 79
• Ram Memory Size: 48KB
• Cpu Speed: 64MHz
• No. Of Timers: 6
• Rohs Compliant: Yes
• Processor Series: ATSAM3x
• Core: ARM Cortex M3
• 3rd Party Development Tools: JTRACE-CM3, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: ATSAM3S-EK
• Cpu Family: AT91
• Device Core: ARM Cortex-M3
• Device Core Size: 32b
• Frequency (max): 64MHz
• Total Internal Ram Size: 48KB
• # I/os (max): 79
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.62V
• On-chip Adc: 16-chx12-bit
• On-chip Dac: 2-chx12-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

26.11 Fast Startup
6500C–ATARM–8-Feb-11
The device allows the processor to restart in less than 10 microseconds while the device is in
Wait mode. The system enters Wait mode either by writing the WAITMODE bit at 1 in the PMC
Clock Generator Main Oscillator Register (CKGR_MOR), or by executing the WaitForEvent
(WFE) instruction of the processor while the LPM bit is at 1 in the PMC Fast Startup Mode Reg-
ister (PMC_FSMR). Waiting for MOSCRCEN bit to be cleared is strongly recommended to
ensure that the core will not execute undesired instructions.
Important: Prior to asserting any WFE instruction to the processor, the internal sources of
wakeup provided by RTT, RTC and USB must be cleared and verified too that none of the
enabled external wakeup inputs (WKUP) hold an active polarity.
A Fast Startup is enabled upon the detection of a programmed level on one of the 16 wake-up
inputs (WKUP) or upon an active alarm form the RTC, RTT and USB Device Controller. The
polarity of the 16 wake-up inputs is programmable by writing the PMC Fast Startup Polarity Reg-
ister (SUPC_FSPR).
The Fast Restart circuitry, as shown in
startup signal to the Power Management Controller. As soon as the fast startup signal is
asserted, this automatically restarts the embedded 4/8/12 MHz Fast RC oscillator.
Figure 26-4. Fast Startup Circuitry
Each wake-up input pin and alarm can be enabled to generate a Fast Startup event by writing at
1 the corresponding bit in the Fast Startup Mode Register SUPC_FSMR.
WKUP15
WKUP0
WKUP1
RTT Alarm
RTC Alarm
USB Alarm
FSTP0
FSTP1
FSTP15
FSTT0
FSTT1
FSTT15
RTTAL
RTCAL
USBAL
Figure
26-4, is fully asynchronous and provides a fast
SAM3S Preliminary
fast_restart
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