ST72F561K9TA STMicroelectronics, ST72F561K9TA Datasheet - Page 122

• Manufacturer Part Number: ST72F561K9TA
• Description: IC MCU 8BIT 60K FLASH 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561K9TA

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST72561
10.7 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE)
10.7.1 Introduction
The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.
The LIN-dedicated features support the LIN (Local
Interconnect Network) protocol for both master
and slave nodes.
This chapter is divided into SCI Mode and LIN
mode sections. For information on general SCI
communications, refer to the SCI mode section.
For LIN applications, refer to both the SCI mode
and LIN mode sections.
10.7.2 SCI Features
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– Address bit (MSB)
– Idle line
Full duplex, asynchronous communications
NRZ standard format (Mark/Space)
Independently programmable transmit and
receive baud rates up to 500K baud
Programmable data word length (8 or 9 bits)
Receive buffer full, Transmit buffer empty and
End of Transmission flags
2 receiver wake-up modes:
Muting function for multiprocessor configurations
Separate enable bits for Transmitter and
Receiver
Overrun, Noise and Frame error detection
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10.7.3 LIN Features
– LIN Master
– LIN Slave
6 interrupt sources
– Transmit data register empty
– Transmission complete
– Receive data register full
– Idle line received
– Overrun error
– Parity interrupt
Parity control:
– Transmits parity bit
– Checks parity of received data byte
Reduced power consumption mode
– 13-bit LIN Synch Break generation
– Automatic Header Handling
– Automatic baud rate resynchronization based
– Automatic baud rate adjustment (at CPU fre-
– 11-bit LIN Synch Break detection capability
– LIN Parity check on the LIN Identifier Field
– LIN Error management
– LIN Header Timeout
– Hot plugging support
on recognition and measurement of the LIN
Synch Field (for LIN slave nodes)
quency precision)
(only in reception)