ST72F561K9TA STMicroelectronics, ST72F561K9TA Datasheet - Page 188

• Manufacturer Part Number: ST72F561K9TA
• Description: IC MCU 8BIT 60K FLASH 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561K9TA

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST72561
beCAN CONTROLLER (Cont’d)
Workaround
To implement the workaround, use the following
sequence to release the CAN receive FIFO.
This sequence replaces any occurrence of
CRFR |= B_RFOM;.
Figure 110. Workaround 1
Explanation of Workaround 1
First, we need to make sure no interrupt can occur
between the test and the release of the FIFO to
avoid any added delay.
The workaround checks if the first two FIFO levels
are already full (FMP = 2) as the problem happens
only in this case.
If FMP ≠ 2 we release the FIFO immediately, if
FMP = 2, we monitor the reception status of the
cell.
The reception status is available in the CMSR reg-
ister bit 5 (REC bit). Note: The REC bit was called
RX in older versions of the datasheet.
– If the cell is not receiving, then REC bit in CMSR
– If the cell is receiving, it is important to make sure
We could simply wait for the end of the reception,
but this could take a long time (200µs for a 100-bit
188/265
if ((CRFR & 0x03) == 0x02)
CRFR |= B_RFOM;
if ((CRFR & 0x03) == 0x02)
while
CRFR |= B_RFOM;
is at 0, the software can release the FIFO imme-
diately: there is no risk.
the release of the mailbox will not happen at the
time when the received message is loaded into
the FIFO.
_WHILELOOP:
_RELEASE:
while
(( CMSR & 0x20) && ( CDGR & 0x08) )
(( CMSR & 0x20) && ( CDGR & 0x08) )
ld
and
cp
jrne
btjf
btjt
bset
a, CRFR
a,#3
a,#2
_RELEASE
CMSR,#5,_RELEASE
CDGR,#3,_WHILELOOP
CRFR,#5
Cycles
frame at 500 kHz), so we also monitor the Rx pin
of the microcontroller to minimize the time the ap-
plication may wait in the while loop.
We know the critical window is located at the end
of the frame, 6+ CAN bit times after the acknowl-
edge bit (exactly six full bit times plus the time from
the beginning of the bit to the sample point). Those
bits represent the acknowledge delimiter + the end
of frame slot.
We know also that those 6+ bits are in recessive
state on the bus, therefore if the CAN Rx pin of the
device is at ‘0’, (reflecting a CAN dominant state
on the bus), this is early enough to be sure we can
release the FIFO before the critical time slot.
Therefore, if the device hardware pin Rx is at 0
and there is a reception on going, its message will
be transferred to the FIFO only 6+ CAN bit times
later at the earliest (if the dominant bit is the ac-
knowledge) or later if the dominant bit is part of the
message.
Compiled with Cosmic C compiler, the workaround
generates the following assembly lines:
{ };
3
2
2
3
5
5
5
test: 10 cycles
loop: 10 cycles
release: 5 cycles
{ };