ST72F561K9TA STMicroelectronics, ST72F561K9TA Datasheet - Page 173

• Manufacturer Part Number: ST72F561K9TA
• Description: IC MCU 8BIT 60K FLASH 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561K9TA

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

beCAN CONTROLLER (Cont’d)
10.9.3.3 Low Power Mode (Sleep)
To reduce power consumption, beCAN has a low
power mode called Sleep mode. This mode is en-
tered on software request by setting the SLEEP bit
in the CMCR register. In this mode, the beCAN
clock is stopped. Consequently, software can still
access the beCAN registers and mailboxes but the
beCAN will not update the status bits.
Example: If software requests entry to initializa-
tion mode by setting the INRQ bit while beCAN is
in sleep mode, it will not be acknowledged by the
hardware, INAK stays cleared.
beCAN can be woken up (exit Sleep mode) either
by software clearing the SLEEP bit or on detection
of CAN bus activity.
On CAN bus activity detection, hardware automat-
ically performs the wake-up sequence by clearing
the SLEEP bit if the AWUM bit in the CMCR regis-
ter is set. If the AWUM bit is cleared, software has
to clear the SLEEP bit when a wake-up interrupt
occurs, in order to exit from sleep mode.
Note: If the wake-up interrupt is enabled (WKUIE
bit set in CIER register) a wake-up interrupt will be
generated on detection of CAN bus activity, even if
the beCAN automatically performs the wake-up
sequence.
After the SLEEP bit has been cleared, Sleep mode
is exited once beCAN has synchronized with the
CAN bus, refer to
Modes. The sleep mode is exited once the SLAK
bit has been cleared by hardware.
10.9.3.4 Test Mode
Test mode can be selected by the SILM and LBKM
bits in the CDGR register. These bits must be con-
figured while beCAN is in Initialization mode. Once
test mode has been selected, beCAN is started in
Normal mode.
10.9.3.5 Silent Mode
The beCAN can be put in Silent mode by setting
the SILM bit in the CDGR register.
In Silent mode, the beCAN is able to receive valid
data frames and valid remote frames, but it sends
only recessive bits on the CAN bus and it cannot
start a transmission. If the beCAN has to send a
dominant bit (ACK bit, overload flag, active error
flag), the bit is rerouted internally so that the CAN
Core monitors this dominant bit, although the CAN
bus may remain in recessive state. Silent mode
can be used to analyze the traffic on a CAN bus
Figure 3. beCAN Operating
without affecting it by the transmission of dominant
bits (Acknowledge Bits, Error Frames).
Figure 97. beCAN in Silent Mode
10.9.3.6 Loop Back Mode
The beCAN can be set in Loop Back Mode by set-
ting the LBKM bit in the CDGR register. In Loop
Back Mode, the beCAN treats its own transmitted
messages as received messages and stores them
(if they pass acceptance filtering) in the FIFO.
Figure 98. beCAN in Loop Back Mode
This mode is provided for self-test functions. To be
independent of external events, the CAN Core ig-
nores acknowledge errors (no dominant bit sam-
pled in the acknowledge slot of a data / remote
frame) in Loop Back Mode. In this mode, the be-
CAN performs an internal feedback from its Tx
output to its Rx input. The actual value of the CAN-
RX input pin is disregarded by the beCAN. The
transmitted messages can be monitored on the
CANTX pin.
beCAN
beCAN
CANTX CANRX
CANTX CANRX
Tx
=1
Tx
Rx
Rx
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