ST72F561K9TA STMicroelectronics, ST72F561K9TA Datasheet - Page 194

• Manufacturer Part Number: ST72F561K9TA
• Description: IC MCU 8BIT 60K FLASH 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561K9TA

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST72561
beCAN CONTROLLER (Cont’d)
Bit 4 = TXOK0 Transmission OK for mailbox 0
- Read
This bit is set by hardware when the transmission
request on mailbox 0 has been completed suc-
cessfully. Please refer to
This bit is cleared by hardware when mailbox 0 is
requested for transmission or when the software
clears the RQCP0 bit.
Bits 3:2 = Reserved. Forced to 0 by hardware.
Bit 1 = RQCP1 Request Completed for Mailbox 1
- Read/Clear
This bit is set by hardware to signal that the last re-
quest for mailbox 1 has been completed. The re-
quest could be a transmit or an abort request.
This bit is cleared by software.
Bit 0 = RQCP0 Request Completed for Mailbox 0
- Read/Clear
This bit is set by hardware to signal that the last re-
quest for mailbox 0 has been completed. The re-
quest could be a transmit or an abort request.
This bit is cleared by software.
CAN TRANSMIT PRIORITY REGISTER (CTPR)
All bits of this register are read only.
Reset Value: 0000 1100 (0Ch)
Bit 7 = Reserved. Forced to 0 by hardware.
Bit 6 = LOW1 Lowest Priority Flag for Mailbox 1
- Read
This bit is set by hardware when more than one
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7
0
LOW1
LOW0
0
Figure
TME1
7.
TME0
0
CODE
0
mailbox are pending for transmission and mailbox
1 has the lowest priority.
Bit 5 = LOW0 Lowest Priority Flag for Mailbox 0
- Read
This bit is set by hardware when more than one
mailbox are pending for transmission and mailbox
0 has the lowest priority.
Note: These bits are set to zero when only one
mailbox is pending.
Bit 4 = Reserved. Forced to 0 by hardware.
Bit 3 = TME1 Transmit Mailbox 1 Empty
- Read
This bit is set by hardware when no transmit re-
quest is pending for mailbox 1.
Bit 2 = TME0 Transmit Mailbox 0 Empty
- Read
This bit is set by hardware when no transmit re-
quest is pending for mailbox 0.
Bit 1:0 = CODE Mailbox Code
- Read
In case at least one transmit mailbox is free, the
code value is equal to the number of the next
transmit mailbox free.
In case all transmit mailboxes are pending, the
code value is equal to the number of the transmit
mailbox with the lowest priority.