ST72F561K9TA STMicroelectronics, ST72F561K9TA Datasheet - Page 128

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ST72F561K9TA

Manufacturer Part Number
ST72F561K9TA
Description
IC MCU 8BIT 60K FLASH 32-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72F561K9TA

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
CAN, LINSCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
497-8374 - BOARD DEVELOPMENT FOR ST72F561
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
10.7.5.4 Conventional Baud Rate Generation
The baud rates for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:
with:
PR = 1, 3, 4 or 13 (see SCP[1:0] bits)
TR = 1, 2, 4, 8, 16, 32, 64,128
(see SCT[2:0] bits)
RR = 1, 2, 4, 8, 16, 32, 64,128
(see SCR[2:0] bits)
All these bits are in the SCIBRR register.
Example: If f
PR = 13 and TR = RR = 1, the transmit and re-
ceive baud rates are 38400 baud.
Note: The baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.
128/265
Tx =
(16
f
CPU
*
PR)
CPU
*
TR
is 8 MHz (normal mode) and if
Rx =
(16
f
CPU
*
PR)
*
RR
10.7.5.5 Extended Baud Rate Generation
The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.
The extended baud rate generator block diagram
is described in
The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
SCIERPR or the SCIETPR register.
Note: The extended prescaler is activated by set-
ting the SCIETPR or SCIERPR register to a value
other than zero. The baud rates are calculated as
follows:
with:
ETPR = 1, ..., 255 (see SCIETPR register)
ERPR = 1, ..., 255 (see SCIERPR register)
Tx =
16
*
ETPR*(PR*TR)
f
CPU
Figure
3.
Rx =
16
*
ERPR*(PR*RR)
f
CPU

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