ST72F561K9TA STMicroelectronics, ST72F561K9TA Datasheet - Page 150

• Manufacturer Part Number: ST72F561K9TA
• Description: IC MCU 8BIT 60K FLASH 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561K9TA

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

ST72561
LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Mode) (cont’d)
LIN PRESCALER FRACTION REGISTER
(LPFR)
Read/Write
Reset Value: 00 00 0000 (00h)
Bits 7:4 = Reserved.
Bits 3:0 = LPFR[3:0] Fraction of LDIV
These 4 bits define the fraction of the LIN Divider
(LDIV):
1. When initializing LDIV, the LPFR register must
be written first. Then, the write to the LPR register
150/265
7
0
LPFR[3:0]
Eh
0h
1h
Fh
...
0
0
0
Fraction (LDIV)
LPFR
3
14/16
15/16
1/16
...
0
LPFR
2
LPFR
1
LPFR
0
0
will effectively update LDIV and so the clock gen-
eration.
2. In LIN Slave mode, if the LPR[7:0] register is
Examples of LDIV coding:
Example 1: LPR = 27d and LPFR = 12d
This leads to:
Mantissa (LDIV) = 27d
Fraction (LDIV) = 12/16 = 0.75d
Therefore LDIV = 27.75d
Example 2: LDIV = 25.62d
This leads to:
LPFR = rounded(16*0.62d)
= rounded(9.92d) = 10d = Ah
LPR = mantissa (25.620d) = 25d = 1Bh
Example 3: LDIV = 25.99d
This leads to:
LPFR = rounded(16*0.99d)
= rounded(15.84d) = 16d
equal to 00h, the transceiver and receiver input
clocks are switched off.