ST72F561K9TA STMicroelectronics, ST72F561K9TA Datasheet - Page 155

• Manufacturer Part Number: ST72F561K9TA
• Description: IC MCU 8BIT 60K FLASH 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F561K9TA

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LINSCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• For Use With: 497-8374 - BOARD DEVELOPMENT FOR ST72F561
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

LINSCI™ SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
10.8.4 Functional Description
The block diagram of the Serial Control Interface,
is shown in
en dedicated registers:
– Three control registers (SCICR1, SCICR2 and
– A status register (SCISR)
– A baud rate register (SCIBRR)
– An extended prescaler receiver register (SCIER-
– An extended prescaler transmitter register (SCI-
Refer to the register descriptions in
10.7.8for the definitions of each bit.
Figure 89. Word Length Programming
SCICR3)
PR)
ETPR)
CLOCK
CLOCK
9-bit Word length (M bit is set)
Start
Figure 88 on page
Bit
8-bit Word length (M bit is reset)
Start
Bit
Bit0
Bit0
Bit1
Bit1
Data Frame
Data Frame
Idle Frame
Break Frame
Break Frame
Idle Frame
153. It contains sev-
Bit2
Bit2
Bit3
Bit3
Section
Bit4
Bit4
Bit5
Bit5
10.8.4.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Transmission and reception are driven by their
own baud rate generator.
Bit6
Bit6
Possible
Bit7
Parity
Figure
Bit7
Bit
** LBCL bit controls last data clock pulse
****
** LBCL bit controls last data clock pulse
Possible
**
Parity
Bit8
Bit
**
Stop
Bit
89).
Stop
Bit
Extra
Start
Next
Start
Bit
Bit
’1’
Next Data Frame
Next
Start
Extra
Start
Bit
Bit
’1’
Start
Bit
Next Data Frame
Start
Bit
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