MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 131

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

14.4 Instruction Set Summary
Freescale Semiconductor
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
BCC rel
BCLR n opr
BCS rel
BEQ rel
BHCC rel
BHCS rel
BHI rel
Source
Form
Add with Carry
Add without Carry
Logical AND
Arithmetic Shift Left
(Same as LSL)
Arithmetic Shift Right
Branch if Carry Bit
Clear
Clear Bit n
Branch if Carry Bit Set
(Same as BLO)
Branch if Equal
Branch if Half-Carry
Bit Clear
Branch if Half-Carry
Bit Set
Branch if Higher
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Operation
Table 14-6. Instruction Set Summary (Sheet 1 of 6)
PC ← (PC) + 2 + rel ? C ∨ Z = 0
PC ← (PC) + 2 + rel ? C = 0
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? H = 0
PC ← (PC) + 2 + rel ? H = 1
PC ← (PC) + 2 + rel ? Z = 1
C
A ← (A) + (M) + (C)
b7
b7
A ← (A) + (M)
A ← (A) ∧ (M)
Description
Mn ← 0
.
b0
b0
0
C
— —
— —
— —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
— — — — —
H
—
—
on CCR
I
Effect
N Z C
—
Instruction Set Summary
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
IMM
EXT
IMM
EXT
IMM
EXT
REL
REL
REL
REL
REL
REL
DIR
DIR
DIR
DIR
INH
INH
DIR
INH
INH
IX2
IX1
IX2
IX1
IX2
IX1
IX1
IX1
IX
IX
IX
IX
IX
AB
BB
CB
DB
EB
A9
B9
C9
D9
E9
F9
FB
A4
B4
C4
D4
E4
F4
1B
1D
1F
38
48
58
68
78
37
47
57
67
77
24
11
13
15
17
19
25
27
28
29
22
ee ff
ee ff
ee ff
hh ll
hh ll
hh ll
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
dd
rr
rr
rr
rr
rr
rr
ff
ff
ff
ff
ff
ii
ii
ii
2
3
4
5
4
3
2
3
4
5
4
3
2
3
4
5
4
3
5
3
3
6
5
5
3
3
6
5
3
5
5
5
5
5
5
5
5
3
3
3
3
3
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