MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 65

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.3.9 PB7/SCK Logic
The PB7/SCK pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as
shown in
When using the PB7/SCK pin, these interactions must be noted:
Freescale Semiconductor
1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB7/SCK
2. If the SIOP function is in control of the PB7/SCK pin, the DDRB7 and PB7 data register bits are still
3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored
4. If the PB7/SCK pin is to be a digital input, then both the SPE bit in the SCR and the DDRB7 bit
pin buffer to be controlled by the MSTR control bit in the SCR. The pulldown device is disabled in
these cases.
accessible to the CPU and can be altered or read without affecting the SIOP functionality.
However, if the DDRB7 bit is cleared, reading the PB7 data register will return the current state of
the PB7/SCK pin.
in the DDRB7, PDIB7, and PB7 register bits will then control the PB7/SCK pin.
must be cleared. Depending on the external application, the pulldown device may also be disabled
by setting the PDIB7 pulldown inhibit bit.
a. If the MSTR bit is set, then the PB7/SCK pin buffer will be enabled and driven by the serial
b. If the MSTR bit is clear, then the PB7/SCK pin buffer will be disabled, allowing the PB7/SCK
Figure
data clock (SCK) from the SIOP.
pin to drive the serial data clock (SCK) into the SIOP.
WRITE $0005
WRITE $0001
WRITE $0011
7-12. The operations of the PB7/SCK pin are summarized in
RESET
READ $0005
READ $0001
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
SERIAL DATA CLOCK (SCK)
CLOCK SOURCE (MSTR)
SERIAL ENABLE (SPE)
R
R
Figure 7-12. PB7/SCK Pin I/O Circuit
PORT B DATA
REGISTER
DATA DIRECTION
BIT PB7
REGISTER B
REGISTER B
PULLDOWN
BIT DDRB7
BIT PDIB7
MASK OPTION REG. ($1FF1)
Table
7-3.
PULLDOWN
DEVICE
SCK
PB7
Port B
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