MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 25

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Freescale Semiconductor
1. Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
Addr.
$1FEF
$001A
$001B
$001C
$001D
$001E
$001F
$1FF0
$0018
$0019
↓
Programmable Timer Register High
Programmable Timer Register Low
See pages
Alternate Counter Register High
Alternate Counter Register Low
EPROM Programming Register
COP and Security Register
Analog Counter Register
Register
Analog Status Register
27, 92, 104, and 122.
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
See page 107.
See page 107.
See page 108.
See page 108.
See page 119.
See page 77.
See page 77.
(EPROG)
Reserved
Reserved
Figure 2-3. Register Summary (Sheet 3 of 3)
(TMRH)
(COPR)
(ACRH)
(TMRL)
(ACRL)
(ACR)
(ASR)
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write: EPMSEC
Bit 7
Bit 15
Bit 15
Bit 15
CPF2
CHG
Bit 7
R
R
1
1
1
1
0
0
0
0
= Unimplemented
ATD2
CPF1
OPT
14
14
14
6
R
R
R
1
6
1
1
1
0
0
0
0
CPFR2
ATD1
13
13
13
5
R
R
R
1
5
1
1
1
0
0
0
0
0
Unaffected by reset
CPFR1
ICEN
12
12
12
4
R
R
R
R
1
4
1
1
1
0
0
0
0
0
= Reserved
COE1
CPIE
11
11
11
3
R
R
R
1
3
1
1
1
0
0
0
0
CP2EN
VOFF
ELAT
10
10
10
R
R
U = Unaffected
2
1
2
1
1
1
0
0
0
Input/Output Registers
CP1EN
MPGM
CMP2
R
R
1
9
1
1
0
9
1
9
0
0
0
0
EPGM
CMP1
COPC
Bit 0
ISEN
Bit 8
Bit 0
Bit 8
Bit 8
R
R
R
1
0
1
0
0
0
0
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