MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 63

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

7.3.7 PB5/SDO Logic
The PB5/SDO pin can be used as a simple I/O port pin or be controlled by the SIOP serial interface as
shown in
When using the PB5/SDO pin, these interactions must be noted:
Freescale Semiconductor
1. If the SIOP function is required, then the SPE bit in the SCR must be set. This causes the PB5/SDO
2. If the SIOP function is in control of the PB5/SDO pin, the DDRB5 and PB5 data register bits are
3. If the SIOP function is terminated by clearing the SPE bit in the SCR, then the last conditions stored
4. If the PB5/SDO pin is to be a digital input, then both the SPE bit in the SCR and the DDRB5 bit
5. If the PB5/SDO pin is to be a digital output, then the SPE bit in the SCR must be cleared and the
pin buffer to be enabled and to be driven by the serial data output (SDO) from the SIOP. The
pulldown device will be disabled in this case.
still accessible to the CPU and can be altered or read without affecting the SIOP functionality.
However, if the DDRB5 bit is cleared, reading the PB5 data register will return the current state of
the PB5/SDO pin.
in the DDRB5, PDIB5, and PB5 register bits will then control the PB5/SDO pin.
must be cleared. Depending on the external application, the pulldown device may also be disabled
by setting the PDIB5 pulldown inhibit bit.
PDIB5 bit must be set. The pulldown device will be disabled in this case.
Figure
WRITE $0005
WRITE $0001
WRITE $0011
READ $0005
READ $0001
RESET
7-10. The operations of the PB5 pin are summarized in
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
SERIAL DATA OUT (SDO)
SERIAL ENABLE (SPE)
R
R
Figure 7-10. PB5/SDO Pin I/O Circuit
PORT B DATA
REGISTER
DATA DIRECTION
BIT PB5
REGISTER B
REGISTER B
PULLDOWN
BIT DDRB5
BIT PDIB5
V
MASK OPTION REG. ($1FF1)
DD
Table
7-3.
PULLDOWN
DEVICE
SDO
PB5
Port B
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