MCHC705JJ7CPE Freescale Semiconductor, MCHC705JJ7CPE Datasheet - Page 134

• Manufacturer Part Number: MCHC705JJ7CPE
• Description: IC MCU 8BIT 224 BYTES RAM 20PDIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MCHC705JJ7CPE

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SIO
• Peripherals: POR, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 6KB (6K x 8)
• Program Memory Type: OTP
• Ram Size: 224 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: HC705JJ
• Core: HC05
• Data Bus Width: 8 bit
• Data Ram Size: 224 B
• Interface Type: SIOP
• Maximum Clock Frequency: 2.1 MHz
• Number Of Programmable I/os: 14
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 4 Channel
• Package: 20PDIP
• Family Name: HC05
• Maximum Speed: 2.1 MHz
• Operating Supply Voltage: 3.3|5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Instruction Set
134
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NOP
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
Source
Form
Jump to Subroutine
Load Accumulator with
Memory Byte
Load Index Register
with Memory Byte
Logical Shift Left
(Same as ASL)
Logical Shift Right
Unsigned Multiply
Negate Byte
(Two’s Complement)
No Operation
Logical OR
Accumulator with
Memory
Rotate Byte Left
through Carry Bit
MC68HC705JJ7 • MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
Operation
Table 14-6. Instruction Set Summary (Sheet 4 of 6)
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCH); SP ← (SP) – 1
Push (PCL); SP ← (SP) – 1
PC ← Conditional Address
0
C
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
C
X : A ← (X) × (A)
b7
b7
A ← (A) ∨ (M)
Description
b7
A ← (M)
X ← (M)
b0
b0
b0
C
0
— — — — —
— —
— —
— —
— — 0
— —
— — — — —
— —
— —
H
0 — — — 0
on CCR
I
Effect
N Z C
—
—
—
⋅
Freescale Semiconductor
EXT
IMM
EXT
IMM
EXT
IMM
EXT
DIR
DIR
DIR
DIR
INH
INH
DIR
INH
INH
INH
DIR
INH
INH
INH
DIR
DIR
INH
INH
IX2
IX1
IX2
IX1
IX2
IX1
IX1
IX1
IX1
IX2
IX1
IX1
IX
IX
IX
IX
IX
IX
IX
IX
CD
DD
BD
ED
FD
AE
BE
CE
DE
EE
AA
BA
CA
DA
EA
A6
B6
C6
D6
E6
F6
FE
9D
FA
38
48
58
68
78
34
44
54
64
74
42
30
40
50
60
70
39
49
59
69
79
ee ff
ee ff
ee ff
ee ff
hh ll
hh ll
hh ll
hh ll
dd
dd
dd
dd
dd
dd
dd
ff
ff
ff
ff
ff
ff
ff
ff
ii
ii
ii
ii
11
5
6
7
6
5
2
3
4
5
4
3
2
3
4
5
4
3
5
3
3
6
5
5
3
3
6
5
5
3
3
6
5
2
2
3
4
5
4
3
5
3
3
6
5