R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 110
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
10.4.3
Table 10.4
Key Input Interrupt
INT0 to INT3 Interrupt
Timer RA Interrupt
Serial Interface Interrupt
Voltage Monitor 2 Interrupt
CAN0 Wake-Up Interrupt
10.4.3.1
10.4.3.2
10.4.3.3
Since the oscillator circuits stop in wait mode, the CPU clock and peripheral function clock stop and the CPU
and peripheral functions clocked by these clocks stop operating. The least power required to operate the MCU
is in stop mode. If the voltage applied to the VCC pin is VRAM or more, the internal RAM is maintained.
The peripheral functions clocked by external signals maintain operating.
Table 10.4 lists Interrupts to Exit Stop Mode and Usage Conditions.
The MCU enters stop mode by setting the CM10 bit in the CM1 register to 1 (all clocks stop). At the same
time, the CM06 bit in the CM0 register is set to 1 (divide-by-8 mode) and the CM15 bit in the CM10 register is
set to 1 (drive capability HIGH of XIN clock oscillator circuit).
When using stop mode, set the OCD1 to OCD0 bits to 00b before entering stop mode.
The status before entering wait mode is maintained.
However, when the CM13 bit in the CM1 register is set to 1 (XIN-XOUT pins), the XOUT(P4_7) pin is held
“H”. When the CM13 bit is set to 0 (input port P4_6 and P4_7), the P4_7(XOUT) is held in input status.
The MCU exits stop mode by a reset or peripheral function interrupt.
When using a reset to exit stop mode, set the ILVL2 to ILVL0 bits for the peripheral function interrupts to 000b
(disables interrupts) before setting the CM10 bit to 1.
Figure 10.12 shows the Time from Stop Mode to Interrupt Routine Execution.
When using a peripheral function interrupt to exit stop mode, set up the following before setting the CM10 bit
to 1.
If the clock used immediately before stop mode is a system clock and stop mode is exited by a peripheral
function interrupt, the CPU clock becomes the previous system clock divided by 8.
(1) Set the interrupt priority level to the ILVL2 to ILVL0 bits of the peripheral function interrupts to use for
(2) Set the I flag to 1.
(3) Operates the peripheral function to use for exiting stop mode.
Stop Mode
exiting stop mode. Set the ILVL2 to ILVL0 bits of the peripheral function interrupts not to use for
exiting stop mode to 000b (disables interrupt).
When exiting by a peripheral function interrupt, the interrupt sequence is executed when an interrupt
request is generated and the CPU clock supply is started.
Entering Stop Mode
Pin Status in Stop Mode
Exiting Stop Mode
Interrupts to Exit Stop Mode and Usage Conditions
Interrupt
Page 88 of 501
Can be used if there is no filter
When there is no filter and external pulse is counted in event
−
counter mode
When external clock is selected
Usable in digital filter disabled mode (VW2C1 bit in VW2C register
is set to 1)
Usable in CAN sleep mode
Usage Conditions
10. Clock Generation Circuit
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