R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 97
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 10.4
Oscillation Stop Detection Register
b7 b6 b5 b4
NOTES:
0 0 0 0
1.
2.
3.
4.
5.
6.
7.
Set the PRC0 bit in the PRCR register to 1 (enables w riting) before rew riting to the OCD register.
Set the OCD1 to OCD0 bits to 00b before entering stop and high-speed on-chip oscillator mode, low -speed on-chip
oscillator mode (XIN clock stops). Set the OCD1 to OCD0 bits to 00b w hen the FRA01 bit in the FRA0 register is set to
1 (selects high-speed on-chip oscillator).
The CM14 bit is set to 0 (low -speed on-chip oscillator on) if the OCD2 bit is set to 1 (selects on-chip oscillator clock).
The OCD2 bit is automatically set to 1 (selects on-chip oscillator clock) if a XIN clock oscillation stop is detected w hile
the OCD1 to OCD0 bits are set to 11b. If the OCD3 bit is set to 1 (XIN clock stops), the OCD2 bit remains unchanged
w hen w riting 0 (selects XIN clock).
The OCD3 bit is enabled w hen the OCD0 bit is set to 1 (oscillation stop detection function enabled).
The OCD3 bit remains 0 (XIN clock oscillates) if the OCD1 to OCD0 bits are set to 00b.
Refer to Figure 10.14 Procedure for Sw itching Clock Source from Low -Speed On-Chip Oscillator to XIN
Clock for the sw itching procedure w hen the XIN clock re-oscillates after detecting an oscillation stop.
b3 b2 b1 b0
OCD Register
Bit Symbol
(b7-b4)
Symbol
OCD0
OCD1
OCD2
OCD3
Page 75 of 501
OCD
—
Oscillation stop detection enable
bit
Oscillation stop detection
interrupt enable bit
System clock select bit
Clock monitor bit
Reserved bits
(7)
(1)
Address
Bit Name
000Ch
(5,6)
(4)
0 : Oscillation stop detection function
1 : Oscillation stop detection function enabled
0 : Disable
1 : Enable
0 : Selects XIN clock
1 : Selects on-chip oscillator clock
0 : XIN clock oscillates
1 : XIN clock stops
Set to 0
disabled
(2)
(2)
After Reset
00000100b
Function
(7)
10. Clock Generation Circuit
(3)
RW
RW
RW
RW
RW
RO
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