R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 262
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.92
Timer RD Status Register i (i = 0 or 1)
b7 b6 b5 b4
NOTES:
1.
2.
3.
Nothing is assigned to the bit 5 in the TRDSR0 register. When w riting to the bit 5, w rite 0. When reading, its content is
1.
The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and w riting 0 to the same bit.
• This bit remains unchanged even if the read result is 0 and w riting 0 to the same bit. (This bit remains 1 even if this
• This bit remains unchanged w hen w riting 1.
Including w hen the BFji (j = C or D) bit in the TRDMR register is set to 1 (TRDGRji is used as the buffer register).
bit is set to 1 from 0 after reading, and w riting 0.)
b3 b2
Registers TRDSR0 to TRDSR1 in Complementary PWM Mode
b1 b0
Bit Symbol
(b7 - b6)
TRDSR0
TRDSR1
Symbol
Page 240 of 501
IMFA
IMFB
IMFC
IMFD
OVF
UDF
—
Input capture/compare match flag A
Input capture/compare match flag B
Input capture/compare match flag C
Input capture/compare match flag D
Overflow flag
Underflow flag
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
Address
Bit Name
(1)
0143h
0153h
Write 0 after read.
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRAi
register.
Write 0 after read.
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRBi
register.
Write 0 after read.
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRCi
register.
Write 0 after read.
[Source for setting this bit to 1]
When the value in the TRDi register
matches w ith the value in the TRDGRDi
register.
Write 0 after read.
[Source for setting this bit to 1]
When the TRDi register overflow s.
[Source for setting this bit to 0]
Write 0 after read.
[Source for setting this bit to 1]
When the TRD1 register underflow s.
[Source for setting this bit to 0]
[Source for setting this bit to 0]
[Source for setting this bit to 0]
[Source for setting this bit to 0]
[Source for setting this bit to 0]
(3)
(3)
After Reset
11100000b
11000000b
Function
(2)
(2)
(2)
(2)
(2)
(2)
14. Timers
RW
RW
RW
RW
RW
RW
RW
—
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