R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 367

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.41
16.3.4
16.3.4.1
When setting the FS bit in the SAR register to 1, the clock synchronous serial format is used to communicate.
Figure 16.41 shows the Transfer Format of Clock Synchronous Serial Format.
When the MST bit in the ICCR1 register is set to 1, the transfer clock is output from the SCL pin and when the
MST bit is set to 0, the external clock is input.
The transfer data is output between the fall and the following fall of the SCL clock, and data is determined by
the rise of the SCL clock. The MSB-first or LSB-first can be selected for the order of the data transfer by setting
the MLS bit in the ICMR register. The SDA output level can be changed by the SDAO bit in the ICCR2 register
during the transfer standby.
Clock Synchronous Serial Mode
SCL
SDA
Clock Synchronous Serial Format
Transfer Format of Clock Synchronous Serial Format
Page 345 of 501
b0
b1
b2
b3
b4
b5
16. Clock Synchronous Serial Interface
b6
b7