R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 127
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 12.6
Address bus
12.1.6.4
CPU clock
Data bus
An interrupt sequence is performed between an interrupt request acknowledgement and interrupt routine
execution.
When an interrupt request is generated while an instruction is executed, the CPU determines its interrupt
priority level after the instruction is completed. The CPU starts the interrupt sequence from the following
cycle. However, in regards to the SMOVB, SMOVF, SSTR or RMPA instruction, if an interrupt request is
generated while executing the instruction, the MCU suspends the instruction to start the interrupt sequence.
The interrupt sequence is performed as follows.
Figure 12.6 shows the Time Required for Executing Interrupt Sequence.
After the interrupt sequence is completed, the instructions are
NOTES:
NOTE:
WR
RD
(1) The CPU gets interrupt information (interrupt number and interrupt request level) by reading the
(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU internal
(3) The I, D and U flags in the FLG register are set as follows:
(4) The CPU’s internal temporary register
(5) The PC is saved to the stack.
(6) The interrupt priority level of the acknowledged interrupt is set in the IPL.
(7) The starting address of the interrupt routine set in the interrupt vector is stored in the PC.
1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the instruction queue
buffer is ready to acknowledge instructions.
1. This register cannot be used by user.
2. For operations of the IR bit, refer to 12.6 Timer RD Interrupt, Clock Synchronous Serial I/O with
address 00000h. The IR bit for the corresponding interrupt is set to 0 (interrupt not requested)
temporary register
The I flag is set to 0 (disables interrupts).
The D flag is set to 0 (disables single-step interrupt).
The U flag is set to 0 (ISP selected).
However, the U flag does not change state if an INT instruction for software interrupt number 32 to 63
is executed.
Chip Select Interrupts and I
Request Sources).
1
Interrupt Sequence
Time Required for Executing Interrupt Sequence
2
Address
0000h
information
Interrupt
3
Page 105 of 501
4
(1)
.
5
Indeterminate
Indeterminate
Indeterminate
6
2
7
C bus Interface Interrupts (Interrupts with Multiple Interrupt
8
(1)
SP-2 SP-1
is saved to the stack.
9
contents
SP-2
10
contents
SP-1
SP-4
11
contents
SP-4
12
SP-3
contents
SP-3
13
VEC
14
contents
VEC
15
VEC+1
contents
VEC+1
16
17
VEC+2
contents
VEC+2
18
12. Interrupts
19
(2)
PC
.
20
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