R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 281
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.109 Block Diagram of Timer RD Interrupt
14.3.11 Timer RD Interrupt
Table 14.35
Channel 0
Channel 1
Timer RD generates the Timer RD interrupt request based on 6 sources every channel. The Timer RD interrupt
has 1 TRDiIC register (IR bit, ILVL0 to ILVL2 bits) every channel, and 1 vector.
Table 14.35 lists the Registers Associated with Timer RD Interrupt and Figure 14.109 shows the Block Diagram
of Timer RD Interrupt.
As with other maskable interrupts, the timer RD interrupt is controlled by the combination of the I flag, IR bit,
bits ILVL0 to ILVL2, and IPL. However, since the interrupt source (timer RD interrupt) is generated by a
combination of multiple interrupt request sources, the following differences from other maskable interrupts
apply:
• When bits in the TRDSRi register corresponding to bits set to 1 in the TRDIERi register are set to 1 (enable
• When either bits in the TRDSRi register or bits in the TRDIERi register corresponding to bits in the
• When the conditions of other request sources are met, the IR bit remains 1.
• When multiple bits in the TRDIERi register are set to 1, which request source causes an interrupt is
• Since each bit in the TRDSRi register is not automatically set to 0 even if the interrupt is acknowledged, set
interrupt), the IR bit in the TRDiIC register is set to 1 (interrupt requested).
TRDSRi register, or both of them, are set to 0, the IR bit is set to 0 (interrupt not requested). Therefore,
even though the interrupt is not acknowledged after the IR bit is set to 1, the interrupt request will not be
maintained.
determined by the TRDSRi register.
each bit to 0 in the interrupt routine. For information on how to set these bits to 0, refer to the descriptions
of the registers used in the different modes (Figures 14.41, 14.56, 14.69, 14.81, 14.92 and 14.104).
Registers Associated with Timer RD Interrupt
i = 0 or 1
IMFA, IMFB, IMFC, IMFD, OVF, UDF: Bits in TRDSRi register
IMIEA, IMIEB, IMIEC, IMIED, OVIE: Bits in TRDIER register
TRDSR0
TRDSR1
OVIE bit
Page 259 of 501
UDF bit
OVF bit
Channel i
Status Register
Timer RD
IMIEC bit
IMIED bit
IMIEA bit
IMIEB bit
IMFC bit
IMFD bit
IMFA bit
IMFB bit
TRDIER0
TRDIER1
Interrupt Enable Register
Timer RD
Timer RD (channel i)
Interrupt request
(IR bit in TRDiIC register)
TRD0IC
TRD1IC
Interrupt Control Register
Timer RD
14. Timers
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