R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 335
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.17
(4)
(5)
(1)
(2)
(3)
(6)
NOTE:
1. Write 0 after reading 1 to set the TEND bit to 0.
SSSR register
SSER register
Communication Mode)
Sample Flowchart of Data Transmission/Reception (Clock Synchronous
Write transmit data to SSTDR register
Read receive data in SSRDR register
Read TDRE bit in SSSR register
Read RDRF bit in SSSR register
Read TEND bit in SSSR register
No
Page 313 of 501
Data transmit
Initialization
continued?
TDRE=1 ?
RDRF=1 ?
TEND=1 ?
Start
End
TEND bit ← 0
RE bit ← 0
TE bit ← 0
Yes
Yes
No
Yes
No
No
(1)
Yes
(2) Confirm that the RDRF bit is set to 1. If the RDRF
(3) Determine whether the transmit data is continued.
(4) When the data transmit is completed, the TEND
(5) Set the TEND bit to 0 and
(6) the RE and TE bits in the SSER register to 0 before
(1) After reading the SSSR register and confirming
bit is set to 1, read the receive data in the SSRDR
register. When reading the SSRDR register, the
RDRF bit is automatically set to 0.
bit in the SSSR register is set to 1.
ending transmit/receive mode.
that the TDRE bit is set to 1, write the transmit
data in the SSTDR register. When writing the
transmit data to the SSTDR register, the TDRE bit
is automatically set to 0.
16. Clock Synchronous Serial Interface
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