R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 547
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (6Mb)
Rev.
1.10
REVISION HISTORY
Oct 31, 2007
Date
Page
363
364
366
367
401
403
404
407
411
412
413
415
420
421
422
423
424
425
427
429
430
432
433
435
439
447
448
449
Figure 17.8; Bit name in the TRAMR register:
“MOD0 to 2 bits” → “Bits TMOD0 to TMOD2”
Figure 17.9; Procedure of Hardware LIN Clear the status flags:
“LINST register ← 0” → “LINST register ← 1”
Figure 17.11; Bit name in the LINST register:
“SCDCT flag” → “BCDCT flag”
Figure 17.12; Procedure of Hardware LIN Clear the status flags:
“LINST register ← 0” → “LINST register ← 1”
Figure 19.2; NOTE4 revised.
Table 19.2; Stop Condition revised.
Figure 19.4; NOTE4 revised.
Figure 19.6; NOTE4 revised.
Figure 19.10 revised. SW5 added.
19.6; the six line from the bottom:
“A/D conversion mode with” → “A/D conversion mode without”
19.7 revised.
Table 20.2; Function of CPU Rewrite Mode:
“any area other than the flash memory” → “the RAM”
Figure 20.4; NOTE1 revised.
Table 20.3; EW1 Mode:
“ROM area” → “ROM or RAM area”
20.4.1 and 20.4.2;
“td(SR-ES)” → “td(SR-SUS)”
20.4.2.4; the third line from the top:
“in other than the flash memory” → “transferred to the RAM”
20.4.2.15 revised.
Figure 20.5; NOTE3 and NOTE5 revised.
Figure 20.7; NOTE5 revised.
Figure 20.9;
“any area other than the flash memory” → “the RAM”
Figure 20.11;
• “any area other than the flash memory” → “the RAM”
• “15us” → “30us”
• NOTE4 deleted.
20.4.3.4 revised.
Figure 20.13 revised and NOTE4 added.
Figure 20.15 revised and NOTE4 added.
Table 20.7; MODE pin revised.
Table 21.1 and Table 21.2 NOTE1; D version added.
Table 21.3 NOTE1; D version added.
Table 21.4; NOTE1 revised.
R8C/22 Group, R8C/23 Group Hardware Manual
C - 24
Description
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