R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 542
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Rev.
1.00
REVISION HISTORY
Oct 27, 2006
Date
Page
293
321
348
357
361
362
364
372
373
374
376
377
404
408
410
413
414
Figure 16.3 SSCRL Register; NOTE2 revised
Figure 16.23 External Circuit Connection Example of Pins SCL and SDA
revised.
Figure 16.47 Example of Register Setting in Master Receive Mode (I
Interface Mode);
corrected.
Figure 17.5 Example of Header Field Transmission Flowchart (1);
Hard ware LIN Clear the status flags; “~ in LINST register” → “~ in LINST
register: 0” corrected.
Figure 17.9 Example of Header Field Reception Flowchart (2);
“When the SBE bit in the LINCR register is 0(Unmasked after Synch Break is
detected), timer RA is usable in timer mode after the SBDCT flag in the LINST
register is set to 1.” added.
Figure 17.10 Example of Header Field Reception Flowchart (3);
“When the SBE bit in the LINCR register is 1 (Unmasked after Synch Field
measurement is completed), timer RA is usable in timer mode after the SFDCT
flag in the LINST register is set to 1.” added.
17.4.4 Hardware LIN End Processing and Figure 17.12 Example of Hardware
LIN Communication Completion Flowchart added.
Figure 18.6 C0MCTLi Register;
Figure 18.7 C0CTLR Register;
Figure 18.8 C0STR Register;
Figure 18.10 C0ICR Register;
Figure 18.11 C0IDR Register;
Figure 18.12 C0CONR Register;
Figure 19.6 ADCON0 Register in Repeat Mode, in the Function of Frequency
select bit 0;
Figure 19.10 Internal Equivalent Circuit of Analog Input;
19.7 Notes on A/D Converter, on the 5th line from the bottom;
20.2 Memory Map, on the 4th line from the bottom;
“When rewriting the block 2 and block 3 in CPU rewrite mode, set the FMR02 bit
in the FMR0 register to 1 (rewrite enables).” added.
Figure 20.1 Flash Memory Block Diagram for R8C/22 Group revised.
(1) “Set the ~ master receive mode ~”→ “Set the ~ master transmit mode ~”
NOTE1 revised.
NOTES revised.
NOTE1 revised.
NOTE1 revised.
NOTE1 revised.
“CAN0 Configuration Register” → “CAN0 Configuration Register
NOTE2 added.
“1: Select fOCO-F” → “Do not set” revised.
“i = 4” → “i = 12” corrected.
“Do not select the fOCO-F for the φAD.” added.
R8C/22 Group, R8C/23 Group Hardware Manual
C - 19
Description
Summary
(2)
” added.
2
C Bus
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