R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 347
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.24
IIC Bus Control Register 1
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
5.
6.
Set according to the necessary transfer rate in master mode. Refer to Table 16.6 Transfer Rate Exam ples for the
transfer rate. This bit is used for maintaining of the setup time in transmit mode. The time is 10Tcyc w hen the CKS3
bit is set to 0 and 20Tcyc w hen the CKS3 bit is set to 1. (1Tcyc = 1/f1(s))
Rew rite the TRS bit betw een the transfer frame.
When the first 7 bits, after the start condition in slave receive mode, match w ith the slave address set in the SAR
register and the 8th bit is set to 1, the TRS bit is set to 1.
In master mode w ith the I
slave receive mode.
When an overrun error occurs in master receive mode of the clock synchronous serial format, the MST bit is set to 0
and the IIC enters slave receive mode.
In multimaster operation use the MOV instruction to set bits TRS and MST.
b3 b2
ICCR1 Register
b1
b0
Bit Symbol
Symbol
ICCR1
RCVD
CKS0
CKS1
CKS2
CKS3
Page 325 of 501
TRS
MST
ICE
2
C bus format, w hen arbitration is lost, the MST and TRS bits are set to 0 and the IIC enters
Transmit clock select bit 3 to
0
Transfer / receive select
bit
Master / slave select bit
Receive disable bit
I
2
(1)
C bus interface enable bit
(2,3,6)
Address
Bit Name
00B8h
(5,6)
b3 b2 b1 b0
0 0 0 0 : f1/28
0 0 0 1 : f1/40
0 0 1 0 : f1/48
0 0 1 1 : f1/64
0 1 0 0 : f1/80
0 1 0 1 : f1/100
0 1 1 0 : f1/112
0 1 1 1 : f1/128
1 0 0 0 : f1/56
1 0 0 1 : f1/80
1 0 1 0 : f1/96
1 0 1 1 : f1/128
1 1 0 0 : f1/160
1 1 0 1 : f1/200
1 1 1 0 : f1/224
1 1 1 1 : f1/256
b5 b4
0 0 : Slave receive mode
0 1 : Slave transmit mode
1 0 : Master receive mode
1 1 : Master transmit mode
After reading the ICDRR register w hile the TRS bit
is set to 0
0 : Maintains the follow ing receive operation
1 : Disables the follow ing receive operation
0 : This module is halted
1 : This module is enabled for transfer
(SCL and SDA pins are set to port function)
(SCL and SDA pins are bus drive state)
operations
16. Clock Synchronous Serial Interface
After Reset
Function
00h
(4)
RW
RW
RW
RW
RW
RW
RW
RW
RW
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