R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 536
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/38/123822/r5f21238dfp_u0_sml.jpg)
R5F21238DFP#U0
Manufacturer Part Number
R5F21238DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21238DFP#U0
Core Size
16/32-Bit
Program Memory Size
64KB (64K x 8)
Peripherals
POR, Voltage Detect, WDT
Core Processor
R8C
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Number Of I /o
41
Program Memory Type
FLASH
Ram Size
3K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
4
Digital Ic Case Style
LQFP
Embedded Interface Type
CAN, I2C, UART
Rohs Compliant
Yes
Cpu Family
R8C
Device Core Size
16b
Frequency (max)
20MHz
Interface Type
I2C/UART
Total Internal Ram Size
3KB
# I/os (max)
41
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
12-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 536 of 551
- Download datasheet (6Mb)
Rev.
1.00
REVISION HISTORY
Oct 27, 2006
Date
47 to 53 Figure 7.1 to Figure 7.3 Configuration of Programmable I/O Ports;
Page
13
14
15
29
30
33
34
35
38
55
66
71
5
6
Table 1.3 Product Information for R8C/22 Group;
Figure 1.2 Type Number, Memory Size, and Package of R8C/22 Group;
Table 1.4 Product Information for R8C/23 Group;
Figure 1.3 Type Number, Memory Size, and Package of R8C/23 Group;
Figure 3.1 Memory Map of R8C/22 Group revised.
Figure 3.2 Memory Map of R8C/23 Group revised.
Table 4.1 SFR Information (1)
bit in the OFS register is 0.” revised.
Table 5.2 Title of Table revised
Figure 5.4 OFS Register;
5.2 Power-On Reset Function
Figure 5.7 Example of Power-On Reset Circuit and Operation revised.
5.3 Voltage Monitor 1 Reset, on the 9th line;
the LVD1ON bit in the OFS register to 0, bits VW1C0 and VW1C6 in the VW1C
register to 1, the VCA bit in the VCA2 register to 1.” added.
5.4 Voltage Monitor 2 Reset;
6. Voltage Detection Circuit;
Figure 6.4 Registers VCA1 and VCA2;
Figure 7.9 PDi (i = 0 to 4 and 6) Registers;
Figure 7.10 Pi (i = 0 to 4 and 6) Registers;
Table 7.42 Port P6_2/CRX0;
“CRX0 output” → “CRX0 input” revised.
Table 10.1 Specifications of Clock Generation Circuit;
“R5F2122AJFP (D)”, “R5F2122CJFP (D)”, “R5F2122AKFP (D)”,
“R5F2122CKFP (D)”, and NOTE added.
“A: 96 KB” and “C: 128 KB” added.
“R5F2123AJFP (D)”, “R5F2123CJFP (D)”, “R5F2123AKFP (D)”,
“R5F2123CKFP (D)”, and NOTE added.
“A: 96 KB” and “C: 128 KB” added.
NOTE8; “The CSPROINI bit in the OFS register is set to 0.” → “The CSPROINI
NOTE2; “LVD0ON” → “LVD1ON” revised.
NOTE1 deleted. NOTE2 revised.
“To use the power-on reset function, enable voltage monitor 1 reset by setting
NOTE1 deleted.
NOTE1 deleted.
NOTE1 deleted.
Voltage Detection Register 2
NOTE5 added.
NOTE1 added
Bit Names revised.
Bit Names revised.
NOTE3; “10 MHz” → “20 MHz” revised.
R8C/22 Group, R8C/23 Group Hardware Manual
C - 13
Description
(1)
(1)
(1)
;
;
revised.
Summary
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