R5F21238DFP#U0 Renesas Electronics America, R5F21238DFP#U0 Datasheet - Page 215

• Manufacturer Part Number: R5F21238DFP#U0
• Description: IC R8C/23 MCU FLASH 48-LQFP
• Manufacturer: Renesas Electronics America
• Series: R8C/2x/23r

Specifications of R5F21238DFP#U0

• Core Size: 16/32-Bit
• Program Memory Size: 64KB (64K x 8)
• Peripherals: POR, Voltage Detect, WDT
• Core Processor: R8C
• Speed: 20MHz
• Connectivity: CAN, I²C, LIN, SIO, SSU, UART/USART
• Number Of I /o: 41
• Program Memory Type: FLASH
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• No. Of I/o's: 41
• Ram Memory Size: 3KB
• Cpu Speed: 20MHz
• No. Of Timers: 4
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Cpu Family: R8C
• Device Core Size: 16b
• Frequency (max): 20MHz
• Interface Type: I2C/UART
• Total Internal Ram Size: 3KB
• # I/os (max): 41
• Number Of Timers - General Purpose: 5
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• On-chip Adc: 12-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 14.46
TRDIOji input signal
14.3.5.1
TRDIOji input signal
Input signal through
fOCO40M
TRDCLK
Sampling clock
The TRDIOji input is sampled, and when the sampled input level matches 3 times, its level is assumed as a
determination. Select the digital filter function and sampling clock by the TRDDFi register.
digital filtering
f32
f8
f4
f2
f1
Clock period selected by the
i = 0 or 1, j = either A, B, C or D
TCK0 to TCK2: Bits in TRDCRi register
DFCK0 to DFCK1 and DFj: Bits in TRDDF register
IOA0 to IOA2 and IOB0 to IOB2: Bits in TRDIORAi register
IOC0 to IOC3 and IOD0 to IOD3: Bits in TRDIORCi register
or DFCK1 to DFCK0 bits
Digital Filter
Block Diagram of Digital Filter
=011b
Timer RD operation clock
TCK2 to TCK0 bits
=100b
=010b
=001b
=101b
D
D
f1, fOCO40M
=000b
Latch
Latch
C
C
TCK2 to TCK0
Page 193 of 501
Q
Q
=110b
Count source
D
f32
f8
f1
Latch
C
=01b
=10b
DFCK1 to DFCK0
=00b
=11b
Transmission cannot be
performed without 3-times match
because the input signal is
assumed as noise.
Q
D
Latch
C
Sampling clock
Q
D
Latch
C
Q
detection
Match
Signal transmission delayed
circuit
up to 5-sampling clock
signal change with
Recognition of the
3-time match
1
0
DFj
Edge detection
IOA2 to IOA0
IOB2 to IOB0
IOC3 to IOC0
IOD3 to IOD0
circuit
14. Timers