DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 189
![IC H8S/2372 MCU FLASH 144LQFP](/photos/12/42/124232/df2372rvfq34v_sml.jpg)
DF2372RVFQ34V
Manufacturer Part Number
DF2372RVFQ34V
Description
IC H8S/2372 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2372RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2372RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 189 of 1208
- Download datasheet (8Mb)
5.4.2
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
• The interrupt priority level can be set by means of IPR.
• The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request.
• When the DMAC or DTC is activated by an interrupt request, it is not affected by the interrupt
5.5
Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority. When interrupt control
mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
IRQn
input
and enable bits that select enabling or disabling of these interrupts. They can be controlled
independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt
controller.
control mode or CPU interrupt mask bit.
Note: n = 15 to 0
Internal Interrupts
Interrupt Exception Handling Vector Table
Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0
IRQnSCA, IRQnSCB
level detection
Edge/
circuit
Clear signal
R
S
IRQnF
Rev.7.00 Mar. 18, 2009 page 121 of 1136
Q
IRQnE
Section 5 Interrupt Controller
REJ09B0109-0700
IRQn interrupt
request
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