DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 832

• Manufacturer Part Number: DF2372RVFQ34V
• Description: IC H8S/2372 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2372RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI, IrDA)
15.9.2
Table 15.14 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt
(TEI) request cannot be used in this mode.
Table 15.14 Interrupt Sources
Channel
0
1
2
3
4
In Smart Card interface mode, as in normal serial communication interface mode, transfer can be
carried out using the DTC or DMAC. In transmit operations, the TDRE flag is also set to 1 at the
same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is
designated beforehand as a DTC or DMAC activation source, the DTC or DMAC will be
activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and
TEND flags are automatically cleared to 0 when data transfer is performed by the DTC or DMAC.
In the event of an error, the SCI retransmits the same data automatically. During this period, the
TEND flag remains cleared to 0 and the DTC or DMAC is not activated. Therefore, the SCI and
DTC or DMAC will automatically transmit the specified number of bytes in the event of an error,
including retransmission. However, the ERS flag is not cleared automatically when an error
occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in
the event of an error, and the ERS flag will be cleared.
Rev.7.00 Mar. 18, 2009 page 764 of 1136
REJ09B0109-0700
Interrupts in Smart Card Interface Mode
Name
TXI4
ERI0
RXI0
TXI0
ERI1
RXI1
TXI1
ERI2
RXI2
TXI2
ERI3
RXI3
TXI3
ERI4
RXI4
Interrupt Source
Transmit Data Empty
Receive Error, detection
Receive Data Full
Transmit Data Empty
Receive Error, detection
Receive Data Full
Transmit Data Empty
Receive Error, detection
Receive Data Full
Transmit Data Empty
Receive Error, detection
Receive Data Full
Transmit Data Empty
Receive Error, detection
Receive Data Full
Interrupt Flag
TEND
ORER, PER, ERS
RDRF
TEND
ORER, PER, ERS
RDRF
TEND
ORER, PER, ERS
RDRF
TEND
ORER, PER, ERS
RDRF
TEND
ORER, PER, ERS
RDRF
Possible
DTC
Activation
Not possible
Possible
Possible
Not possible
Possible
Possible
Not possible
Possible
Possible
Not possible
Possible
Possible
Not possible
Possible
DMAC
Activation
Not possible
Possible
Possible
Not possible
Possible
Possible
Not possible
Not possible
Not possible
Not possible
Not possible
Not possible
Not possible
Not possible
Not possible
Priority
Low
High