DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 846
![IC H8S/2372 MCU FLASH 144LQFP](/photos/12/42/124232/df2372rvfq34v_sml.jpg)
DF2372RVFQ34V
Manufacturer Part Number
DF2372RVFQ34V
Description
IC H8S/2372 MCU FLASH 144LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheet
1.YR0K42378FC000BA.pdf
(1208 pages)
Specifications of DF2372RVFQ34V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
34MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
For Use With
YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2372RVFQ34V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 846 of 1208
- Download datasheet (8Mb)
Section 16 I
Bit
1
0
16.3.3
ICMR controls the master mode wait and selects the number of transfer bits.
Bit
7
6
5, 4
3
Rev.7.00 Mar. 18, 2009 page 778 of 1136
REJ09B0109-0700
Bit Name
IICRST
⎯
Bit Name
MLS
WAIT
⎯
BCWP
I
2
C Bus Mode Register (ICMR)
2
C Bus Interface 2 (IIC2) (Option)
Initial Value
1
Initial Value
0
0
All 1
1
0
R/W
R/W
⎯
R/W
R/W
R/W
⎯
R/W
Description
This bit resets control parts except for I
If this bit is set to 1 when hang-up is occurred
because of communication failure during I
operation, I
setting ports and initializing registers.
Reserved
This bit is always read as 1.
Description
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Wait Insertion Bit
This bit selects whether to insert a wait after data
transfer except for the acknowledge bit. When
WAIT is set to 1, after the fall of the clock for the
final data bit, low period is extended for two transfer
clocks. If WAIT is cleared to 0, data and
acknowledge bits are transferred consecutively with
no wait inserted.
The setting of this bit is invalid in slave mode.
Reserved
These bits are always read as 1.
BC Write Protect
This bit controls the BC2 to BC0 modifications.
When modifying BC2 to BC0, this bit should be
cleared to 0 and use the MOV instruction.
0: When writing, values of BC2 to BC0 are set.
1: When reading, 1 is always read.
IIC control part reset
When writing, settings of BC2 to BC0 are invalid.
2
C control part can be reset without
2
C registers.
2
C
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