DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 773

• Manufacturer Part Number: DF2372RVFQ34V
• Description: IC H8S/2372 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2372RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
3
2
1
0
Note:
Bit Name
PER
TEND
MPB
MPBT
* Only 0 can be written, to clear the flag. Alternately, use the bit clear instruction to clear
the flag.
Initial Value
0
1
0
0
R/W
R/(W) *
R
R
R/W
Section 15 Serial Communication Interface (SCI, IrDA)
Description
Parity Error
Indicates that a parity error occurred while
receiving in asynchronous mode and the reception
has ended abnormally.
[Setting condition]
•
[Clearing condition]
•
Transmit End
[Setting conditions]
•
•
[Clearing conditions]
•
•
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
data. When the RE bit in SCR is cleared to 0 its
previous state is retained.
Multiprocessor Bit Transfer
MPBT sets the multiprocessor bit to be added to
the transmit data.
When a parity error is detected during reception
If a parity error occurs, the receive data is
transferred to RDR but the RDRF flag is not set.
Also, subsequent serial reception cannot be
continued while the PER flag is set to 1. In
clocked synchronous mode, serial transmission
cannot be continued, either.
When 0 is written to PER after reading PER = 1
The PER flag is not affected and retains its
previous state when the RE bit in SCR is
cleared to 0.
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit
of a 1-byte serial transmit character
When 0 is written to TDRE after reading TDRE
= 1
When the DMAC or DTC is activated by a TXI
interrupt and writes data to TDR
Rev.7.00 Mar. 18, 2009 page 705 of 1136
REJ09B0109-0700