DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 55

• Manufacturer Part Number: DF2372RVFQ34V
• Description: IC H8S/2372 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2372RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 15.2 Data Format in Asynchronous Communication
Figure 15.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 725
Figure 15.4 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode). 726
Figure 15.5 Sample SCI Initialization Flowchart ....................................................................... 727
Figure 15.6 Example of Operation in Transmission in Asynchronous Mode
Figure 15.7 Sample Serial Transmission Flowchart ................................................................... 729
Figure 15.8 Example of SCI Operation in Reception
Figure 15.9 Sample Serial Reception Data Flowchart (1) .......................................................... 732
Figure 15.9 Sample Serial Reception Data Flowchart (2) .......................................................... 733
Figure 15.10 Example of Communication Using Multiprocessor Format
Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart .......................................... 736
Figure 15.12 Example of SCI Operation in Reception
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1).......................................... 738
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2).......................................... 739
Figure 15.14 Data Format in Clocked Synchronous Communication (For LSB-First) ................ 740
Figure 15.15 Sample SCI Initialization Flowchart ....................................................................... 741
Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode .................... 742
Figure 15.17 Sample Serial Transmission Flowchart ................................................................... 743
Figure 15.18 Example of SCI Operation in Reception ................................................................. 744
Figure 15.19 Sample Serial Reception Flowchart ........................................................................ 745
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations ........ 747
Figure 15.21 Schematic Diagram of Smart Card Interface Pin Connections................................ 748
Figure 15.22 Normal Smart Card Interface Data Format ............................................................. 749
Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0) ........................................................ 749
Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1)....................................................... 750
Figure 15.25 Receive Data Sampling Timing in Smart Card Mode
Figure 15.26 Retransfer Operation in SCI Transmit Mode .......................................................... 754
Figure 15.27 TEND Flag Generation Timing in Transmission Operation ................................... 754
Figure 15.28 Example of Transmission Processing Flow............................................................. 755
Figure 15.29 Retransfer Operation in SCI Receive Mode ............................................................ 756
Figure 15.30 Example of Reception Processing Flow.................................................................. 757
Figure 15.31 Timing for Fixing Clock Output Level.................................................................... 757
Figure 15.32 Clock Halt and Restart Procedure ........................................................................... 758
Figure 15.33 Block Diagram of IrDA........................................................................................... 759
Figure 15.34 IrDA Transmit/Receive Operations......................................................................... 760
(Example with 8-Bit Data, Parity, Two Stop Bits).................................................. 723
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 728
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 730
(Transmission of Data H'AA to Receiving Station A) ............................................ 735
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)................................ 737
(Using Clock of 372 Times the Bit Rate) ................................................................ 751
Rev.7.00 Mar. 18, 2009 page liii of lxvi
REJ09B0109-0700