DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 809

• Manufacturer Part Number: DF2372RVFQ34V
• Description: IC H8S/2372 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2372RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

15.6.2
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described in a sample flowchart in figure 15.15. Do not write to SMR, SCMR,
IrCR, or SEMR while the SCI is operating. This also applies to writing the same data as the
current register contents. When the operating mode, transfer format, etc., is changed, the TE and
RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE
flag is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER,
FER, and ORER flags, or the contents of RDR.
15.6.3
Figure 15.16 shows an example of SCI operation for transmission in clocked synchronous mode.
In serial transmission, the SCI operates as described below.
SCI Initialization (Clocked Synchronous Mode)
Serial Data Transmission (Clocked Synchronous Mode)
Note: In simultaneous transmit and receive operations, the TE and RE bits should
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
Set data transfer format in
both be cleared to 0 or set to 1 simultaneously.
1-bit interval elapsed?
Start of initialization
Set value in BRR
SMR and SCMR
<Transfer start>
(TE, RE bits 0)
Figure 15.15 Sample SCI Initialization Flowchart
Yes
Wait
No
Section 15 Serial Communication Interface (SCI, IrDA)
[4]
[2]
[3]
[1]
[1] Set the clock selection in SCR. Be sure
[2] Set the data transfer format in SMR
[3] Write a value corresponding to the bit
[4] Wait at least one bit interval, then set
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE, to 0.
and SCMR.
rate to BRR. (Not necessary if an
external clock is used.)
the TE and RE bits in SCR to 1.
Also set the RIE, TIE, TEIE, and MPIE
bits.
Setting the TE and RE bits enable the
TxD and RxD pins to be used.
Rev.7.00 Mar. 18, 2009 page 741 of 1136
REJ09B0109-0700