DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 346

• Manufacturer Part Number: DF2372RVFQ34V
• Description: IC H8S/2372 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2372RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
6.14.4
When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before
the BACK signal.
This will occur if the next external access request or CBR refresh request occurs while internal bus
arbitration is in progress after the chip samples a low level of BREQ.
6.14.5
Setting of Synchronous DRAM Interface: The DCTL pin must be fixed to 1 to enable the
synchronous DRAM interface. Do not change the DCTL pin during operation.
Connection Clock: Be sure to set the clock to be connected to the synchronous DRAM to
SDRAMφ.
WAIT Pin: In the continuous synchronous DRAM space, insertion of the wait state by the WAIT
pin is disabled regardless of the setting of the WAITE bit in BCR.
Bank Control: This LSI cannot carry out the bank control of the synchronous DRAM. All banks
are selected.
Burst Access: The burst read/burst write mode of the synchronous DRAM is not supported.
When setting the mode register of the synchronous DRAM, set to the burst read/single write and
set the burst length to 1.
CAS Latency: When connecting a synchronous DRAM having CAS latency of 1, set the BE bit
to 0 in the DRAMCR.
Note: The synchronous DRAM interface is not supported by the H8S/2378 Group.
Rev.7.00 Mar. 18, 2009 page 278 of 1136
REJ09B0109-0700
BREQO Output Timing
Notes on Usage of the Synchronous DRAM