DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 798

• Manufacturer Part Number: DF2372RVFQ34V
• Description: IC H8S/2372 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2372RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI, IrDA)
15.4.6
Figure 15.8 shows an example of the operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line, and if a start bit is detected, performs internal
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive
5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
Rev.7.00 Mar. 18, 2009 page 730 of 1136
REJ09B0109-0700
RDRF
FER
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
1
Serial Data Reception (Asynchronous Mode)
Start
bit
0
D0
Figure 15.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
D1
1 frame
Data
D7
RXI interrupt
request
generated
Parity
bit
0/1
Stop
bit
1
Start
bit
0
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt handling routine
D0
D1
Data
D7
Parity
bit
ERI interrupt request
generated by framing
error
0/1
Stop
bit
0
Idle state
(mark state)
1