DF2372RVFQ34V Renesas Electronics America, DF2372RVFQ34V Datasheet - Page 450

• Manufacturer Part Number: DF2372RVFQ34V
• Description: IC H8S/2372 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2372RVFQ34V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 34MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• For Use With: YLCDRSK2378 - KIT DEV EVAL H8S/2378 LCDYR0K42378FC000BA - KIT EVAL FOR H8S/2378HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 EXDMA Controller (EXDMAC)
Block Transfer Mode: In block transfer mode, the number of bytes or words specified by the
block size is transferred in response to one transfer request. The upper 8 bits of EDTCR specify
the block size, and the lower 16 bits function as a 16-bit transfer counter. A block size of 1 to 256
can be specified. During transfer of a block, transfer requests for other higher-priority channels are
held pending. When transfer of one block is completed, the bus is released in the next cycle.
When the BGUP bit is set to 1 in EDMDR, the bus is released if a bus request is issued by another
bus master during block transfer.
Address register values are updated in the same way as in normal mode. There is no function for
restoring the initial address register values after each block transfer.
The ETEND signal is output for each block transfer in the DMA transfer cycle in which the block
ends. The EDRAK signal is output once for one transfer request (for transfer of one block).
Rev.7.00 Mar. 18, 2009 page 382 of 1136
REJ09B0109-0700
Transfer conditions:
Transfer conditions:
Bus cycle
ETEND
EDREQ
EDRAK
Bus cycle
EDACK
Dual address mode, auto request mode
Single address mode, external request mode
Figure 8.7 Examples of Timing in Normal Transfer Mode
Read
transfer cycle
EXDMA
Write
EXDMA
Read
Last EXDMA
transfer cycle
EXDMA
Write