UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 342

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note
(Remark is listed on the next page.)
Option byte (000C1H)
FRQSEL2,
FRQSEL1
X2/EXCLK
XT2//P124
XT1/P123
Clock operation mode
X1/P121
/P122
control register
Those are are only mounted in the
AMPHS1
(CMC)
AMPH
Crystal/ceramic
oscillation (1 MHz (TYP.))
oscillation (8 MHz (TYP.))
oscillation (20 MHz (TYP.))
External input
High-speed system
Internal high-speed
Internal high-speed
high-speed oscillator
Internal high-speed
oscillation
Internal high-speed
oscillation
Subsystem clock
clock oscillator
20 MHz internal
EXCLK OSCSEL
Crystal
AMPHS0
clock
oscillator
oscillator
Clock operation mode
control register
(CMC)
OSCSELS
f
f
f
f
IH20
f
f
EX
IH1
IH8
XT
X
Clock operation status
f
f
f
f
MX
IH
IH20
SUB
control register
Clock operation status
oscillation (30 kHz (TYP.))
(CSC)
Internal low-speed
Internal low-speed
CLS
control register
oscillator
MSTOP
μ
Figure 7-3. Block Diagram of Clock Generator (78K0R/KF3-L, 78K0R/KG3-L)
PD78F1027, 78F1028, 78F1029, and 78F1030.
(CSC)
XTSTOP HIOSTOP
STOP mode
signal
f
IL
DSCS
MOST
8
SELDSC
Option byte (000C0H)
WDTON
WDSTBYON
MOST
HALT/STOP mode signal
9
stabilization time counter
OSTS2
MOST
20 MHz internal high-speed
oscillation control register
(DSCCTL)
10
DSCON
X1 oscillation
Internal bus
MOST
Internal bus
OSTS1 OSTS0
11
MOST
3
13
Oscillation stabilization
time counter status
register (OSTC)
Oscillation stabilization
time select register (OSTS)
MOST
15
MOST
17
MOST
18
Main system clock
source selector
SAU
2EN
Peripheral enable
register 1
f
Note
MAIN
(PER1)
RTC
EN
CLS
Clock output/
buzzer output
ADC
EN
CSS
f
f
f
f
f
f
f
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
SUB
/2
/2
/2
/2
/2
/2
MCS
IICA
5
4
3
2
EN
MCM0
SAU1
Watchdog timer
Real-time counter,
clock output/buzzer output
EN
Peripheral enable
register 0 (PER0)
1
System clock control
register (CKC)
SAU0
EN
MD
IV2
and peripheral
clock source
CPU clock
hardware
TAU1
selection
EN
4
MD
IV1
TAU0
MD
IV0
EN
f
CLK
Standby controller
operation mode
STOP mode
HALT mode
Normal
CPU
Timer array unit 0
Timer array unit 1
Serial array unit 0
Serial array unit 1
Serial array unit 2
Serial interface IICA
Real-time counter
A/D converter
Note