UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 726

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(2) Operation procedure
Caution
After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more f
Setting the SMRmn register
Setting the SCRmn register
Setting the SDRmn register
Writing to the SSm register
Setting the SPSm register
Setting the PER0 register
Setting the SOm register
Setting the SOm register
Setting the SOm register
Changing setting of the SOEm
Starting communication
Starting initial setting
Figure 14-99. Initial Setting Procedure for Address Field Transmission
Setting port
register
Wait
Set the initial output level of the serial data
(SOmn) and serial clock (CKOmn).
Enable data output, clock output, and N-ch
open-drain output (V
target channel by setting the port register, port
mode register, and port output mode register.
Set the SSmn bit of the target channel to 1 and set
the SEmn bit to 1 (to enable operation).
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the
transfer clock by dividing the operation
clock (f
Clear the SOmn bit to 0 to generate the
start condition.
Secure a wait time so that the specifications of
I
Clear the CKOmn bit to 0 to lower the
clock output level.
Set the SOEmn bit to 1 and enable data
output of the target channel.
Set address and R/W to the SIOr register
(bits 7 to 0 of the SDRmn register) and
start communication.
2
C on the slave side are satisfied.
MCK
)).
CLK
DD
clocks have elapsed.
tolerance) mode of the
CHAPTER 14 SERIAL ARRAY UNIT
726