UPD78F1001GA-HAA-AX Renesas Electronics America, UPD78F1001GA-HAA-AX Datasheet - Page 935

• Manufacturer Part Number: UPD78F1001GA-HAA-AX
• Description: MCU 16BIT 78K0R/KX3-L 44-TQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3-Lr

Specifications of UPD78F1001GA-HAA-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Kx3-L
(1) When LVI is OFF upon power application (option byte: LVIOFF = 1)
R01UH0106EJ0300 Rev.3.00
Oct 01, 2010
(when X1 oscillation
oscillation clock (f
Internal high-speed
Notes 1.
Caution Set the low-voltage detector by software after the reset status is released (see CHAPTER 23 LOW-
Remark V
V
V
Internal reset signal
system clock (f
POR
PDR
= 1.61 V (TYP.)
= 1.59 V (TYP.)
Supply voltage
High-speed
is selected)
1.8 V
6.
2.
3.
4.
5.
CPU
(V
MX
V
Note 1
IH
VOLTAGE DETECTOR).
V
V
0 V
Operation
LVI
DD
)
)
The operation guaranteed range is 1.8 V ≤ V
when the supply voltage falls, use the reset function of the low-voltage detector, or input the low level to the
RESET pin.
If the rate at which the voltage rises to 1.8 V after power application is slower than 0.5 V/ms (MIN.), input a
low level to the RESET pin before the voltage reaches to 1.8 V, or set LVI to ON by default by using an
option byte (option byte: LVIOFF = 0).
The reset processing time, such as when waiting for internal voltage stabilization, includes the oscillation
accuracy stabilization time of the internal high-speed oscillation clock.
The internal reset processing time includes the oscillation accuracy stabilization time of the internal high-
speed oscillation clock.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register
(OSTC) to confirm the lapse of the oscillation stabilization time. To use the XT1 clock
function for confirmation of the lapse of the stabilization time.
The 78K0R/KC3-L (40-pin) doesn’t have the subsystem clock.
LVI
POR
PDR
Figure 22-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
)
stops
:
: POC power supply fall detection voltage
: POC power supply rise detection voltage
LVI detection voltage
Reset processing
Wait for oscillation
accuracy stabilization
(2.12 to 5.84 ms)
0.5 V/ms (MIN.)
specified by software
Starting oscillation is
Note 2
Set LVI to be
used for reset
Note 3
oscillation clock)
(internal high-speed
Normal operation
and Low-Voltage Detector (1/2)
Note 5
(oscillation
Reset
period
stop)
Reset processing (195 to 341 s)
Wait for oscillation
accuracy stabilization
used for interrupt
Set LVI to be
oscillation clock)
(internal high-speed
Normal operation
DD
Starting oscillation is
specified by software
≤ 5.5 V. To make the state at lower than 1.8 V reset state
Note 4
μ
Note 5
CHAPTER 22 POWER-ON-CLEAR CIRCUIT
(oscillation
Reset
period
stop)
Wait for oscillation
accuracy stabilization
Reset processing
(2.12 to 5.84 ms)
specified by software
Starting oscillation is
used for reset
Set LVI to be
Note 3
oscillation clock)
(internal high-speed
Normal operation
Note 6
Note 5
, use the timer
Operation stops
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